Address Multiplexing
Address multiplexing is the technique of sending a memory chip's address in two sequential halves — a row address followed by a column address — over the same set of pins, rather than presenting the entire address at once over a larger number of dedicated pins. It is a foundational part of how dynamic RAM is designed, introduced to volume production in the 4-kilobit DRAM generation and retained, in evolved form, across the memory generations that followed. Its purpose is economic: it reduces the number of pins a memory chip needs, which shrinks the package and lowers cost, at the modest price of a slightly more complex, two-step addressing protocol.
The problem address multiplexing solves is that pin count grows with memory capacity, and pins are expensive, so presenting a full address directly becomes costly as chips get bigger. A memory with many locations needs a wide address to select among them, and providing every address bit its own pin inflates the package size and cost. Multiplexing recognizes that the address can be delivered in pieces over time instead of all at once in parallel: the chip receives the first half, holds it internally, then receives the second half, reconstructing the full address from the two. Trading a little time and some on-chip latching for far fewer pins is almost always a good deal for a dense memory part.
Address multiplexing relies on two control signals, traditionally called the row address strobe and the column address strobe, that tell the chip which half of the address is currently on the pins. When the row strobe is asserted, the chip captures the address bits present as the row address; when the column strobe follows, it captures the next set of bits as the column address. These two strobes and their timing relationship became a defining part of the DRAM interface, so central that the row and column strobe concept is part of the basic vocabulary of memory design, carried forward and refined through many later generations of dynamic memory.
The scheme is a natural fit for how memory arrays are physically built, which is part of why it endured rather than being a temporary hack. A memory chip organizes its cells as a two-dimensional grid of rows and columns; selecting a specific cell inherently means choosing a row and then a column. Address multiplexing mirrors this physical structure directly in the interface — the row address activates a row of the array, and the column address then selects within it — so the two-step protocol is not arbitrary but aligned with the chip's internal organization. That alignment between interface and physical layout is why the approach generalized so well across generations.
Address multiplexing is a clean example of a broader principle in chip design: the interface between a chip and its system is a primary source of cost and value, not a secondary detail. The storage cell is what holds the data, but how the chip is addressed and packaged can dominate its practical cost and usability. By rethinking the addressing protocol, designers lowered memory cost without touching the storage technology at all. This lesson — optimize the boundary, not just the core — recurs throughout semiconductor history, and address multiplexing is one of its most durable and widely copied instances.
Read address multiplexing as the pin-saving bargain at the heart of DRAM: deliver the address in a row half and a column half over shared pins, timed by two strobes, trading a two-step protocol for far fewer pins and a cheaper package, in a scheme that mirrors the memory's own row-and-column structure and outlasted the chips that introduced it.