64k DRAM 1979 Address Pin Count Outgrows the Package

# Why Doubling the Array Four Times Over Threatens to Double the Pins the Package Can't Spare

## 1. State the Pin-Count Arithmetic a Growing Array Forces

Every series this project has produced about DRAM so far — 1968's 1T1C cell, 1974's trench and stacked capacitor scaling — addressed how to store and retain a bit inside a single cell as that cell shrank. None of them addressed a different problem that grows just as fast as the array itself: how an external circuit identifies which one of the array's cells it wants. A memory array of $N$ cells, addressed the straightforward way, needs $\log_2 N$ address lines, each one its own physical pin on the package:

$$n_{addr}=\log_2 N$$

A 16K-bit DRAM needs $\log_2(16384)=14$ address pins. A 64K-bit generation — four doublings later, following the same capacitor-scaling progress the 1974 series documented — needs $\log_2(65536)=16$. Two more pins sounds trivial until it is weighed against what a DRAM package pin actually costs: every pin added increases package size, assembly cost, and the number of bond wires that can fail, on a part whose entire commercial purpose is to be as cheap and small as possible per bit stored. The array itself scaled cleanly, cell by cell, through everything 1968 and 1974 built. The pins used to name an address inside that array did not get the same discount.

Array Capacity Scales Exponentially; Pin Count Scales Logarithmically n_addr = log2(N) — slow growth in pins, but every pin still costs real package area 4K DRAM 12 address pins 16K DRAM 14 address pins 64K DRAM 16 address pins n_addr = log2(N) each doubling of array capacity adds only ONE more address pin but every pin still costs package area, bond wires, and assembly — none of it is free 16 ADDRESS PINS PLUS DATA, POWER, AND CONTROL PINS pushes a 64K-generation DRAM out of the cheap, small, high-volume package this chip needs to be the array scaled; the way we name a cell did not have to stay fixed a given pin can carry two different addresses, at two different times — Section 2

## 2. Show That a Pin Only Has to Carry One Address, Not Address the Whole Array at Once

The constraint above assumes every address bit needs its own dedicated pin for the entire memory cycle. That assumption is not a law of physics — it is a convenience that earlier, smaller DRAM generations never had to question, because 12 or 14 pins fit the package comfortably. A pin is simply an electrical connection; nothing requires it to carry the same logical meaning throughout an access cycle. If an array is organized as a two-dimensional grid of rows and columns, an address can be split into a row component and a column component, and the same physical pins can be reused: row address presented first, then the identical pins repurposed to present the column address a moment later.

$$n_{pins}=\frac{n_{addr}}{2}=\log_2(\sqrt{N})=\frac{1}{2}\log_2 N$$

For 64K's 16-bit address, this halves the pin requirement to 8 — not by changing how many cells the array holds or how many unique addresses exist, but by changing how many of those address bits must be visible on the package at the same instant. This is the governing idea the rest of this series will build out in detail: row and column address strobes, timing, and the sense-amplifier interaction this multiplexing scheme has with the array's own read cycle.

The Same 8 Pins Carry a Row Address, Then a Column Address Real Diagram — one set of address pins, two sequential meanings per cycle TIME SLOT 1: ROW ADDRESS 8 pins present row bits selects which row of the array latched internally by RAS strobe entire row's cells become accessible TIME SLOT 2: COLUMN ADDRESS same 8 pins now present column bits selects which cell within that row latched internally by CAS strobe one specific cell is now fully addressed same wires n_pins = (1/2)·log2(N) 16 address bits become 8 pins carrying two meanings sequentially the array's full addressability is preserved — only the pin-at-a-time budget changes this trades pin count for timing complexity two strobes, two latches, a sequencing requirement — Section 3

## 3. Place This Constraint in the DRAM Lineage and Name What Comes Next

This series picks up a thread the project's two prior DRAM series never had reason to pull. The 1968 series fixed the cell's circuit — one transistor, one capacitor, charge as the stored quantity. The 1974 series fixed the capacitor's geometry as that cell's footprint shrank. Both series worked entirely *inside* the array: nothing about the cell or the capacitor cared how many pins the finished chip exposed to the outside world. This series is the first in the DRAM lineage to work on the array's periphery — the addressing and I/O logic surrounding a cell array whose internal design this project has already thoroughly documented — because peripheral pin count, not cell density, is what threatens to make the next DRAM generation impractical to package.

Address multiplexing is not free. Splitting one address into a row half and a column half demands that something inside the chip track *which* half a given set of pins currently represents, and that the row address be latched, used, and released before the column address can validly follow. That sequencing requirement is new: no series this project has produced needed internal timing logic that distinguishes "this signal means one thing now" from "this signal means something different a moment later" on the same physical pins. Step 2 takes up that requirement directly: the Row Address Strobe and Column Address Strobe signals that tell the chip which meaning its address pins currently carry, and the timing margin between them that the whole scheme depends on.

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