64k-DRAM-1979 Step 10 Ship a Dedicated DRAM Controller Chip
# Ship a Separate Product: the Dedicated DRAM Controller Chip
Step 5 automated refresh scheduling on the memory chip itself; a real, commercially distinct alternative existed at this generation — putting that same scheduling and multiplexing logic into a separate controller chip instead.
## 1. State What a Dedicated Controller Chip Actually Did
A DRAM controller chip, such as Intel's 8203, sat between a host processor and an array of memory chips, generating the multiplexed addresses (Step 1's own architecture), the RAS/CAS sequencing (Steps 2, 9), and the refresh-scheduling signals (Steps 4, 5) that the memory chips themselves consumed as simple inputs — performing, in a separate chip, much of the same logic Step 5 described as living on the memory chip directly.
## 2. State Why Both Approaches Coexisted
On-chip refresh automation (Step 5) reduced the burden on system designers at the cost of area spent on every memory chip, whether or not a given system needed that chip to manage its own refresh independently. A separate controller chip concentrated that logic once, shared across many memory chips in a system, at the cost of needing an additional component and a defined interface between it and the memory array — a tradeoff this project's own `dram_1968` series Step 13 names in the abstract (the external-burden problem) without this series' own on-chip-versus-separate-chip resolution.
## 3. Place Both Approaches in This Series' Own Lineage
Both approaches solve the same problem this series' Steps 4 and 5 identified — refresh must be scheduled and executed somewhere — and the commercial market supported both simultaneously through this generation, rather than one displacing the other outright. The controller-chip approach is a real, named alternative to Step 5's own on-chip automation, not a correction of it.