DRAM-1968 Step 14 Ship the Intel 1103 First Commercial Product

# Ship the First Commercial Product: Intel's 1103, 1970

The architecture this series built through Step 10 existed as IBM research and patent claims through 1968; it became a catalog part any designer could buy in 1970, when Intel shipped the 1103 — and the gap between those two years is its own story.

## 1. State What the 1103 Actually Was

The Intel 1103 was a 1-kilobit (1024-bit) dynamic RAM, the first DRAM sold commercially as a standard part rather than built captively inside one company's own systems. It implemented the same 1T1C architecture this series derived from first principles across Steps 2 through 4 — a MOS access transistor and a MOS storage capacitor, per bit — on a p-channel silicon-gate MOS process. Its headline selling point was exactly the density argument Step 8 of this series measured in the abstract: far more bits per unit area than the magnetic-core and bipolar-latch memory it was pitched to replace.

Ship the First Commercial Product: Intel's 1103, 1970 Step 14 — dram-1968 State What the 1103 Actually Was see Section 1 Confront the Real Reception Problems, Not Just t see Section 2 Place the 1103 in This Series' Lineage Honestly see Section 3 THREE-PART ARGUMENT, ONE STEP dram-1968 extension, step 14 of this project's DRAM lineage

## 2. Confront the Real Reception Problems, Not Just the Theoretical Advantage

The 1103's actual deployment exposed every obligation this series' Steps 5 through 7 had already identified as a cost, now as a concrete system-integration headache rather than an abstract tradeoff: it required three separate supply voltages, its refresh burden (Step 6's interval, Step 13's external-obligation argument) landed entirely on system designers with no prior DRAM experience, and its timing margins were tight enough that several early systems shipped with reliability problems traced directly back to inadequate refresh-timer design — not to any defect in the cell architecture itself. Designers accustomed to core memory's comparatively forgiving timing had to relearn system design around a part whose stored state required continuous, correctly-timed maintenance.

Step 14 in the Dram-1968 Lineage what this step inherits and what it hands forward, by name Step 14 this step Inherits prior steps Hands Off named thread NO CELL-PHYSICS OR ARCHITECTURE RE-ARGUED each step adds a distinct angle; none re-derive settled prior content

## 3. Place the 1103 in This Series' Lineage Honestly

The 1103 is the point where this series' architecture stopped being a laboratory result and became an economic one: density cheap enough, and volume high enough, to displace core memory commercially within a few years of introduction, despite real integration friction at launch. It validates Step 8's area argument and Step 9's density-versus-complexity qualification with real shipped-product evidence rather than the architecture's own internal self-consistency alone — and it is also the direct ancestor of the refresh-automation and address-multiplexing pressure that this project's `dram64k_1979` series treats at the next memory generation, built on a part the 1103 itself did not yet need (1024 bits needed only 10 address lines, not the pin-starved width that forces multiplexing later).

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