DRAM Scaling 1974 Planar Capacitor Area Collapses Under Scaling

# Why a Shrinking Cell Forces the Capacitor Off the Plane: Planar Charge Storage Collapses Under Scaling

## 1. State the Constraint the 1968 Cell Never Had to Face

The 1T1C cell fixes the circuit — one access transistor, one storage capacitor — but it does not fix the capacitor's geometry. Through the mid-1970s, that capacitor was simply a doped region of silicon under a gate electrode, its plates separated by a thin oxide, its stored charge set entirely by how much silicon *area* the layout could spare. As each new process generation shrinks the minimum feature size, that area is exactly what shrinks fastest.

A planar capacitor's capacitance is area over distance:

$$C_s=\varepsilon_{ox}\frac{A}{t_{ox}}, \qquad A\propto F^2$$

Minimum feature size $F$ falls by roughly 0.7× per generation, so a cell laid out entirely in the plane loses capacitor area as $F^2$ — a single generation can cut available area in half, and several generations compound that loss multiplicatively. Thinning the oxide $t_{ox}$ claws back some capacitance per generation, but oxide thinning is bounded by tunneling leakage and by the same reliability limits already pressing on the access transistor's gate. Area, not oxide thickness, is the term that was always going to run out first.

Planar Capacitor Area Falls as F², Required Charge Does Not each generation's cell shrinks faster than a flat capacitor can shed area without losing signal GEN N cell pitch F GEN N+1 0.7F 0.49F2 area SIGNAL CHARGE NEEDED FOR RELIABLE SENSING STAYS ROUGHLY FIXED bit-line capacitance, sense-amp offset, and soft-error margin do not shrink with the cell Cs = εox·A / tox, A ∝ F² flat-plate capacitance falls quadratically; thinning t_ox alone cannot keep pace

## 2. Show Why the Shortfall Is Electrical, Not Cosmetic

Losing capacitor area is not merely a smaller number on a datasheet; it directly degrades the sensing operation the 1968 series built the whole cell around. Reading a 1T1C cell means sharing its stored charge with a much larger bit-line capacitance and letting the sense amplifier detect the resulting voltage step:

$$\Delta V=\frac{C_s}{C_s+C_{bl}}\,V_{dd}$$

$C_{bl}$, set by bit-line length and the number of cells hanging off it, does not shrink just because $C_s$ did. As $C_s$ falls, $\Delta V$ falls with it, and it falls toward the sense amplifier's intrinsic offset and the noise floor set by leakage and alpha-particle soft-error charge. A cell that stores too little charge is not merely slow to read — a single stray ionizing particle can deposit enough charge to flip a bit that was never storing much of a margin to begin with. The retention-time requirement inherited unchanged from the 1968 series,

$$t_{ret}\approx \frac{C_s\,V_{dd}}{I_{leak}}$$

falls in step with $C_s$ as well: less stored charge drains to the same leakage floor in less time, so refresh intervals compress exactly when the memory array is trying to grow larger and slower to refresh completely.

Falling C_s Squeezes Both Sensing Margin and Retention Time Real Diagram — the two failure paths a shrinking planar capacitor opens at once READ PATH ΔV = Cs/(Cs+Cbl) · Vdd C_bl fixed by array geometry C_s falls → ΔV falls approaches sense-amp offset RETENTION PATH tret ≈ Cs·Vdd / Ileak I_leak set by junction, not layout C_s falls → t_ret falls refresh interval compresses BOTH FAILURE PATHS SHARE ONE ROOT CAUSE a flat plate's area was always the one term scaling could not spare the 1968 cell's circuit survives unchanged — the capacitor's geometry cannot the plane is out of area; the fix must leave the plane trench and stacked capacitors recover area in the third dimension — Step 2

## 3. Place This Constraint in the Project's Own Lineage

This is a problem the 1968 series could not have encountered, because it did not need to: Step 2 of that series fixed the cell's *circuit* — storing a bit as charge on a capacitor rather than as a latched state — and that decision never depended on how the capacitor's plates were arranged in space. The 1T1C cell's electrical identity, established there, is preserved completely here; nothing about $Q=CV$ changes. What changes is the one input that circuit decision left unconstrained: capacitor geometry was free to be planar only as long as the plane had area to give.

The shape of this problem is also familiar from further back in the lineage. The 1961 epitaxial series faced a structural limit that no change in doping concentration could resolve, because the limit was geometric — a single uniform substrate could not simultaneously maximize breakdown voltage and minimize collector resistance. Here, no change in oxide thickness or doping can resolve a limit that is also geometric — a single flat plate cannot simultaneously shrink its footprint and hold its charge. In both cases the resolution available within the existing geometry had already been exhausted; in both cases the resolution came from adding a dimension the original structure did not use. The 1961 series answered by growing a layer. This series will answer by leaving the plane: either etching downward into the substrate for a trench capacitor, or building upward over the transistor for a stacked capacitor. Step 2 takes up that choice directly.

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