DRAM Scaling 1974 Fill Trench Without Leaving a Void

# Step 7 — Fill the Trench Without Leaving a Void: Conformal Deposition and the Pinch-Off Limit

## 1. Knudsen Diffusion and the Threat of Premature Pinch-Off

Once a high-aspect-ratio trench is etched into the silicon, the fabricator must coat the sidewalls with dielectric and fill the cavity with conductive polysilicon without allowing the trench mouth to seal prematurely. In Step 3, we treated the trench cavity as an ideal geometric cylinder whose sidewalls provide vertical surface area. Step 6 added the buried plate and oxide collar to isolate the cell electrically. But converting this micro-machined hole into a functional capacitor requires depositing thin films deep inside a cavity whose diameter $d \le 0.5\ \mu\text{m}$ is far smaller than the mean free path of gas molecules at conventional chemical vapor deposition (CVD) pressures.

In such narrow, deep holes ($h \ge 6\ \mu\text{m}$, aspect ratio $\text{AR} \ge 12:1$), gas transport is governed entirely by Knudsen diffusion, where precursor molecules collide predominantly with the trench sidewalls rather than with other gas molecules:

$$D_K = \frac{d}{3}\sqrt{\frac{8 k_B T}{\pi m}}$$

where $d$ is the trench diameter, $T$ is temperature, and $m$ is the molecular mass of the precursor gas. Because gas transport down the high-aspect-ratio channel is severely throttled, the step coverage ($\text{SC} = t_{\text{bottom}} / t_{\text{top}}$) depends on the balance between surface reaction rate $k_s$ and Knudsen diffusion $D_K$, encapsulated by the Thiele modulus:

$$\Phi_L = h \sqrt{\frac{k_s}{D_K \cdot d}}$$

If deposition operates in the transport-limited regime ($\Phi_L \gg 1$), precursor molecules (such as silane $\text{SiH}_4$ or dichlorosilane $\text{SiH}_2\text{Cl}_2$) react and deposit on the upper rim of the trench before diffusing to the floor. The entrance narrows, choking off reactant supply to the lower cavity. The rim eventually touches and welds shut—a catastrophic failure known as pinch-off—trapping an unfilled, hollow keyhole void inside the heart of the storage node.

Trench Fill Dynamics: Pinch-Off vs. Conformal CVD Knudsen diffusion throttling, keyhole void entrapment, and reaction-limited 100% step coverage TRANSPORT-LIMITED: PINCH-OFF VOID Pinch-Off Neck! KEYHOLE VOID High Reaction Rate (ΦL >> 1): • Reactants deplete before reaching bottom of trench • Overhang seals trench; capacitance drops unpredictably • Trapped voids crack silicon during thermal anneals REACTION-LIMITED: 100% CONFORMAL FILL 100% Solid Poly Fill ✓ Zero Voids / Planar Plug Low Pressure LPCVD / a-Si (ΦL << 1): • Low pressure (0.2 Torr) & lower temp (550°C) slows reaction • Precursors diffuse uniformly to floor: 100% step coverage • Solid-phase crystallization yields void-free, robust electrode THE CONFORMAL DEPOSITION CONTROL DISCIPLINE ✓ Temperature and Pressure Throttling: Lowering surface reaction kinetics allows Knudsen diffusion to supply the trench floor ✓ Void Elimination: Conformal amorphous silicon deposition and solid-phase crystallization eliminate keyhole defect sites Step coverage and filling integrity replace planar area as the primary yield-determining variables in high-volume fabs.

## 2. The Physical Consequences of Trapped Voids: Electrical, Mechanical, and Chemical

When void-free deposition fails, the trapped keyhole void creates a triad of distinct physical failure modes that destroy DRAM wafer yield.

The Triad of Void Failure Modes electrical shortfall, thermal stress fracture, and chemical contamination trapping 1. ELECTRICAL DEFICIT Capacitance Collapse • Unfilled volume reduces plate area • Cs drops below 25 fF threshold Series Resistance Spikes • Narrowed neck chokes poly contact • High RC write latency / read failure Fails 1968 sensing margin ΔV floor. 2. THERMAL STRESS CRACKS Stress Concentration • Sharp void apex acts as crack tip • Thermal cycles expand hollow cavity Silicon Dislocations • Generates bulk crystal slip planes • Severe junction leakage drains bit Permanently degrades refresh time. 3. CHEMICAL ENTRAPMENT Trapped Corrosive Byproducts • Cl⁻, F⁻, and H₂ sealed inside void • Outgases during 900°C S/D anneals Subsequent Blistering • Volatiles burst through thin strap • Destroys gate oxide and metal vias Creates latent reliability defects. The Manufacturing Reality of Deep Trenches: Etching the cavity is only half the battle; filling it with zero voids under Knudsen diffusion constraints determines commercial wafer yield.

## 3. Place This Step in the Project's Own Lineage

Step 7 anchors the physical reality of fabricating three-dimensional structures:
1. The Evolution of the Retention-Time Problem: In the 1968 series, retention time was dictated entirely by thermodynamic junction leakage ($I_{\text{leak}} \propto \sqrt{N_A}$) and oxide thinning. Step 7 reveals that once the capacitor enters the third dimension, retention time becomes heavily vulnerable to fabrication defects: a void-induced crystal dislocation or localized series resistance bottleneck can wipe out the cell's storage margin just as completely as bulk leakage.
2. From Planar Geometry to Reaction Kinetics: In planar technology, film thickness was a 1D scalar set by deposition time. In deep trench technology, film thickness becomes a multi-dimensional function of gas dynamics, Knudsen diffusion, and surface reaction kinetics. To achieve a uniform $7\ \text{nm}$ dielectric liner and void-free poly-Si fill, semiconductor fabs were forced to master Low-Pressure Chemical Vapor Deposition (LPCVD) and precursors with ultra-low sticking coefficients.
3. The Mirror Problem in the Stacked Architecture: The trench camp endured extreme Knudsen diffusion and pinch-off hazards precisely to keep the wafer surface planar. In Step 8, we turn back to the stacked capacitor camp to examine its mirror problem: having avoided deep holes, how does the stacked camp flatten the severe vertical mountains it erected above the transistor?

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