electromigration reliability

**Electromigration (EM) Analysis** is the **reliability verification discipline that ensures metal interconnect wires in a chip will survive their intended operational lifetime (typically 10-15 years) without failure — where electromigration, the gradual displacement of metal atoms by electron momentum transfer at high current densities, creates voids (open circuits) and hillocks (short circuits) that cause chips to fail months or years after deployment if current density limits are violated during design**. **The Physics of Electromigration** Current flowing through a metal wire creates an "electron wind" that transfers momentum to metal atoms at grain boundaries and interfaces. Over time, atoms migrate in the direction of electron flow, creating: - **Voids**: Depletion regions where atoms have migrated away. Eventually, an open circuit forms. - **Hillocks**: Accumulation regions where atoms pile up. Can cause short circuits to adjacent wires. The failure rate follows Black's Equation: MTTF = A × (J)^(-n) × exp(Ea/kT), where J is current density, n ≈ 1-2, Ea is activation energy (~0.7-0.9 eV for copper), k is Boltzmann's constant, and T is temperature. Doubling current density reduces lifetime by 2-4x. Increasing temperature by 10°C reduces lifetime by ~2x. **Current Density Limits** Foundries specify maximum allowed current density for each metal layer and via, based on the target lifetime and operating conditions: - **Average (DC) Current Density**: Typically 1-5 MA/cm² for copper, depending on metal width and layer. - **Peak (AC) Current Density**: Higher limits apply for bidirectional (AC) current because atoms migrate in both directions, partially canceling the effect. - **Via Current**: Each via has a maximum current limit. Wide wires must have sufficient vias to distribute current below the per-via limit. **EM Analysis in the Design Flow** 1. **Power Grid EM**: The power distribution network carries the highest sustained currents. IR drop analysis tools (Voltus, RedHawk) simultaneously compute voltage drop and EM violations. Power stripes and via arrays must be sized to keep current density below limits. 2. **Signal EM**: Signal wires carry transient current during switching. Average current depends on switching activity, slew rate, and load capacitance. High-fanout clock nets and reset nets are common signal EM violators. 3. **Clock Tree EM**: Clock buffers drive high-capacitance loads at the toggle rate. Clock net segments near the root carry the highest current and are frequent EM violation sites. **Fixing EM Violations** - **Widen Wires**: Increase metal width to reduce current density. Costs routing resources. - **Add Parallel Straps**: Duplicate wires on adjacent metal layers connected by vias to share current. - **Add Vias**: Multiple vias at transitions between metal layers. Via arrays for wide power connections. - **Reduce Switching Activity**: Clock gating, buffer downsizing, or re-routing to balance current distribution. **Electromigration Analysis is the long-term reliability conscience of chip design** — the verification step that prevents a chip from passing all functional tests today while containing the seeds of failure that would manifest as field returns years after deployment.