electromigration signoff
**Electromigration (EM) Sign-off** is the **reliability verification that ensures no metal interconnect in the chip exceeds the maximum allowed current density**, preventing the gradual atomic displacement of metal atoms by electron flow (electromigration) that would eventually cause open circuits or short circuits during the product's operational lifetime.
Electromigration is a wear-out mechanism: metal atoms in interconnects are slowly pushed by the momentum transfer from conducting electrons ("electron wind"). Over months to years of operation, this atomic migration can create voids (causing opens) at cathode ends and hillocks (causing shorts) at anode ends of metal segments.
**EM Physics and Limits**:
| Factor | Effect on EM | Design Impact |
|--------|-------------|---------------|
| **Current density** | Higher J → faster degradation | Primary design constraint |
| **Temperature** | Exponential acceleration (Arrhenius) | Worst-case is highest temp |
| **Metal width** | Narrow wires have less margin | Routing width constraints |
| **Grain structure** | Bamboo vs. polycrystalline | Affects current limit 2-5x |
| **Barrier metal** | Ta/TaN liner provides blocking | Fabrication-dependent |
**Black's Equation**: Mean Time to Failure (MTTF) = A * J^(-n) * exp(Ea/kT), where J = current density, n = current exponent (typically 1-2), Ea = activation energy (~0.7-0.9 eV for Cu), T = temperature. The exponential temperature dependence means EM lifetime halves roughly every 10-15 degrees Celsius increase.
**EM Rule Categories**: **Average EM** (sustained DC or RMS current — most metal segments); **peak EM** (maximum instantaneous current — typically 2-10x higher limit than average); **RMS EM** (for signals with AC current — clock nets, data buses); and **via EM** (via current carrying capacity, often the weakest point — limited by via resistance and contact area).
**EM Analysis Flow**: The signoff tool (RedHawk/Voltus) extracts current through every metal segment and via from vector-based or vectorless power analysis, computes the effective current density considering duty cycle and waveform shape, and compares against the foundry-provided EM limit table (categorized by metal layer, wire width, temperature, and desired lifetime). Violations are flagged with the specific segment, current value, and limit.
**EM Fix Strategies**: **Widen the wire** (doubling width halves current density — but consumes routing space); **add parallel paths** (split current across multiple wire segments); **increase via count** (double vias reduce per-via current); **reduce driver strength** (if signal timing allows); **metal layer promotion** (upper layers have thicker metal with higher EM limits); and **thermal optimization** (reducing local temperature extends EM lifetime exponentially).
**Electromigration signoff is the guarantee of long-term reliability — a chip that passes all functional and timing requirements at time zero but fails EM checks will develop open or short circuits in the field, making EM verification essential for any product with a multi-year operational lifetime requirement.**