electrostatic discharge protection circuit
**Electrostatic Discharge (ESD) Protection Circuit Design** is the **creation of on-chip protection structures that safely shunt ESD current (up to several amperes for nanoseconds) away from sensitive circuits** while adding minimal parasitic capacitance, leakage, and area. ESD protection must be transparent during normal operation yet activate instantly during discharge.
**ESD Stress Models**:
| Model | Source | Peak Current | Duration |
|-------|--------|-------------|----------|
| **HBM** | Human contact | ~1.3A at 2kV | ~150 ns |
| **CDM** | Package discharge | ~5-15A at 500V | ~1 ns |
| **MM** | Equipment | ~3.5A at 200V | ~40 ns |
| **System IEC** | In-system | ~8-30A at 8-15kV | ~100 ns |
**Primary Clamp Topologies**:
**Grounded-Gate NMOS (GGNMOS)**: The simplest I/O clamp. During ESD, drain-bulk junction avalanches, injecting holes that forward-bias the parasitic NPN. The NPN latches via snapback, providing a low-impedance path. Design: device width, silicide blocking, multi-finger layout with ballasting resistors.
**Silicon Controlled Rectifier (SCR)**: Highest current-per-area efficiency. The PNPN thyristor latches to ~1V holding voltage. Challenge: high trigger voltage requires LVTSCR circuits. SCR's latch-up risk requires careful holding voltage engineering.
**Power Clamp (RC-triggered)**: For VDD-to-VSS protection. An RC network detects fast ESD transients versus normal power ramp. During ESD, the RC output triggers a large NMOS clamp shorting VDD to VSS.
**Advanced Node Challenges**: Sub-7nm FinFET: **reduced breakdown voltages** lower the ESD design window; **CDM becomes dominant** (ultra-thin oxides fail at <5V); **FinFET effects** — discrete fin widths limit W sizing, self-heating degrades current handling; **signal integrity** — high-speed I/Os (>50 Gbps) tolerate only ~50fF total pad capacitance including ESD, forcing T-coil extension or distributed schemes.
**ESD protection is the unsung guardian of IC reliability — its failure during a single nanosecond event permanently destroys a billion-transistor chip.**