epitaxial defect density
**Epitaxial Defect Density** refers to the **crystalline imperfections generated during semiconductor epitaxial growth** — including stacking faults, misfit dislocations, threading dislocations, hillocks, and point defects — where even parts-per-billion-level defectivity can cause transistor failure in modern CMOS, making epi quality control a yield-critical process.
**Epitaxial Defect Classification**:
| Defect Type | Nature | Size | Cause | Impact |
|------------|--------|------|-------|--------|
| **Threading dislocation** | Line defect propagating through film | nm width, μm-mm length | Lattice mismatch | Leakage, reliability |
| **Misfit dislocation** | Line defect at hetero-interface | At interface plane | Strain relaxation | Defect nucleation site |
| **Stacking fault** | Planar defect (wrong layer sequence) | μm² area | Contamination, surface prep | Leakage path, yield killer |
| **Hillock/mound** | Surface protrusion | 10nm-1μm | Growth condition instability | Lithography/CMP issue |
| **Point defects** | Vacancy, interstitial, impurity | Atomic | Thermodynamic equilibrium | Carrier lifetime |
| **Epi haze (surface roughness)** | Micro-roughness | sub-nm RMS | Growth temperature, rate | Gate oxide quality |
**Stacking Faults**: The most common and damaging defect in silicon epitaxy. Formed when: the substrate surface has a contamination particle or damaged site that disrupts the normal ABCABC stacking sequence of {111} planes; pre-existing crystal defects in the substrate propagate into the epi layer; or oxidation-induced stacking faults (OISF) form during subsequent thermal processing. Stacking faults create recombination sites and can act as electrically active leakage paths through junctions.
**Defect Density Targets**:
| Application | Stacking Fault Density | Threading Dislocation Density |
|------------|----------------------|-----------------------------|
| Logic (advanced) | <0.1 /cm² | <100 /cm² |
| DRAM | <0.05 /cm² | <50 /cm² |
| Image sensor | <0.01 /cm² | <10 /cm² |
| Power device (SiC) | N/A | <100-1000 /cm² |
**SiGe Epi for Strain**: Growing SiGe (or SiC) with lattice mismatch introduces strain but also risk of defects. The critical thickness (Matthews-Blakeslee criterion) defines the maximum film thickness before misfit dislocations form to relieve strain. For Si₀.₇Ge₀.₃, critical thickness is ~10-20nm. Exceeding it causes relaxation and threading dislocation generation. Advanced devices carefully design layer stacks to stay below critical thickness at each interface.
**In-Situ Quality Monitoring**: Real-time monitoring of epi quality using: **reflectometry** (thickness and composition during growth), **pyrometry** (temperature uniformity), **mass spectrometry** (residual gas analysis for contamination), and **post-growth inspection** (darkfield wafer inspection with sensitivity to stacking faults and particles). Specification for advanced nodes: <0.05 lightpoint defects/cm² >65nm size (Surfscan).
**Epitaxial defect density is the silent arbiter of semiconductor yield — crystalline imperfections measured in parts per billion that individually destroy transistors and collectively determine whether a wafer produces a profitable number of working chips, making epi quality one of the most demanding precision manufacturing challenges in the industry.**