What Is an Etch Polysilicon Process Iep Endpoint Algorithm

An etch polysilicon process Interferometric Endpoint algorithm (etch polysilicon process IEP endpoint algorithm) is an optical fringe-tracking and phase-inversion metrology system engineered to monitor the real-time thinning of polycrystalline silicon (poly-Si) or amorphous silicon dummy gates during anisotropic reactive ion etching. In replacement metal gate (RMG) architectures and 3D NAND gate patterning, polysilicon must be carved with vertical sidewalls and stopped precisely atop a delicate 1.0 nm to 1.5 nm gate dielectric or pad oxide ($SiO_2 / HfO_2$). While Optical Emission Spectroscopy (OES) only detects when the bulk polysilicon film begins clearing into the oxide stop, an IEP endpoint algorithm tracks the continuous vertical recession nanometer by nanometer throughout the main etch. This enables the etch tool to trigger a "soft landing" transition (switching from an aggressive, high-bias $Cl_2/HBr$ chemistry to a highly selective, low-bias $HBr/O_2$ chemistry) when exactly 5 nm to 10 nm of polysilicon remains, preventing catastrophic gate dielectric punch-through and substrate silicon recess pits. At a high level, how an IEP endpoint algorithm controls a polysilicon gate etch sequence looks like this:

Normal-incidence laser launch
Polarized diode (670nm / 905nm) focused on poly macro
Main etch ignition (Cl2 / HBr)
High etch rate & vertical anisotropic profile
Poly-Si fringe phase tracking loopContinuous fringe counting through optical dispersion
Bulk fringe period counting
Delta d = lambda / (2*n_poly) ~ 85 nm per cycle
Phase unwrapping & velocity
Continuous instantaneous poly thickness calculation
Remaining thickness trigger
Pre-clearing alert at target t_rem = 8 nm
↻ track poly thickness
Soft-landing transition
Switch to low-bias HBr/O2 (>150:1 selectivity to oxide)
Pristine gate oxide preservation
Zero recess pit & sub-1nm gate oxide retention

A few principles are essential for understanding how IEP endpoint algorithms govern polysilicon etching, why grain structure affects optical refractive index, and how multi-step recipe handoffs prevent gate oxide breakdown:

Grain morphology and temperature modify the optical refractive index ($n, k$). Polycrystalline silicon exhibits grain-boundary scattering and temperature-dependent complex refractive index values: $\tilde{n} = n - ik$. At room temperature, crystalline silicon has $n \approx 3.88$ at 670 nm, but heavily doped, fine-grained poly-Si at typical wafer chuck temperatures (50°C to 70°C) exhibits an effective index of $n_{\text{poly}} \approx 4.05\text{ to }4.15$ with non-zero extinction coefficient $k \approx 0.05$. Therefore, one complete peak-to-peak interference cycle corresponds to:

$$\Delta d_{\text{fringe}} = \frac{\lambda_0}{2 n_{\text{poly}}} \approx \frac{670\text{ nm}}{2 \times 4.10} \approx 81.7\text{ nm}$$

If an algorithm uses static single-crystal silicon optical constants, calculated remaining thickness will drift by 4 nm to 6 nm. Leading-edge IEP algorithms utilize dynamic Run-to-Run (R2R) temperature-compensated dispersion tables and calibrate $n_{\text{poly}}$ across the first two bulk interference fringes, recalculating the exact local fringe period before reaching the critical interface.

The two-stage recipe handoff: main etch to soft landing. Etching polysilicon directly onto an ultra-thin 1.2 nm gate oxide using a single aggressive plasma chemistry is impossible. The high RF substrate bias needed to maintain vertical gate profiles ($Cl_2/HBr/CF_4$) would punch through the oxide within 200 milliseconds, gouging the underlying silicon channel. The IEP algorithm solves this through a deterministic two-stage recipe transition:
1. *Stage 1 (Main Etch IEP Tracking):* High-bias $Cl_2/HBr$ plasma etches bulk poly at 250 nm/min. The IEP algorithm tracks sinusoidal interference cycles, continuously decrementing the remaining thickness $d_{\text{poly}}(t)$.
2. *Stage 2 (Soft-Landing Trigger):* When the unwrapped phase reaches the pre-programmed specification corresponding to exactly $d_{\text{rem}} = 8.0\text{ nm}$, the IEP algorithm triggers an instant hardware interrupt.
3. *Stage 3 (Low-Bias Over-Etch):* The tool switches instantaneously to an ultra-selective $HBr/O_2/He$ chemistry. Oxygen forms a passivating $SiO_xBr_y$ layer on exposed oxide, raising selectivity over $SiO_2$ from 20:1 to $>150:1$. The remaining 8 nm of poly clears gently without damaging the gate dielectric.

Polysilicon Etch IEP Endpoint Algorithm & Soft-Landing bulk fringe tracking, pre-clearing phase trigger, and ultra-thin gate oxide preservation Polysilicon Gate Recess SiN Hardmask Poly-Si Gate (n_poly ≈ 4.10) Receding Poly 8nm Poly Remainder Gate Oxide (SiO2 / HfO2, 1.2nm) Single-Crystal Si Substrate Dynamic IEP Reflectance & Recipe Step Transition Main Etch (Cl2/HBr) High Bias Soft Landing (HBr/O2) IEP TRIGGER (8nm Rem) Fringe 1 Fringe 2 Soft Landing Clear Process Time (s) → Reflectance Temperature Index Tracking Dynamic n_poly(T) compensation 8nm Soft-Landing Handoff Pre-clearing trigger before oxide Zero Channel Recess Loss Preserves 1.2nm gate dielectric polysilicon IEP algorithms trigger the soft-landing recipe before the gate oxide stop layer is reached dynamic index calibration and phase unwrapping guarantee sub-nanometer gate dielectric retention

Phase inversion detection at the oxide interface. As the polysilicon film recedes below a quarter wavelength ($d_{\text{poly}} < \lambda / 4n_{\text{poly}} \approx 20\text{ nm}$), the optical behavior undergoes a critical shift:
- *Refractive Index Boundary:* Polysilicon ($n \approx 4.10$) has a substantially higher refractive index than the underlying silicon dioxide ($n \approx 1.46$). At the poly-$SiO_2$ boundary, reflection undergoes zero phase change, whereas reflection at the top vacuum-poly boundary undergoes a $180^\circ$ ($\pi$) phase shift.
- *Phase Inversion Slope:* As thickness approaches zero ($d \rightarrow 0$), reflected intensity approaches an absolute minimum or maximum depending on the optical thickness of the underlying gate oxide. The IEP algorithm monitors the sign of the first derivative $dI/dt$: when $dI/dt$ flattens into the terminal phase-inversion plateau, the algorithm calculates the exact remaining nanometers, verifying that the main etch terminates before the first atomic monolayer of oxide is struck by energetic $Cl^+$ ions.

Mitigating poly grain roughness and doping variability. Highly doped n-type ($As, P$) or p-type ($B$) polysilicon exhibits grain boundaries ranging from 10 nm to 50 nm across the wafer. During plasma etching, halogen radials etch along grain boundaries slightly faster than crystalline grain cores, creating microscopic surface faceting. This micro-roughness causes progressive attenuation of the reflected interference fringes. IEP algorithms apply dynamic envelope normalization:

$$I_{\text{norm}}(t) = \frac{I(t) - I_{\text{mid}}(t)}{A_{\text{envelope}}(t)}$$

By dividing by the decaying envelope amplitude $A_{\text{envelope}}(t)$ in real time, the algorithm restores a normalized $\pm 1$ sinusoidal signal, ensuring robust fringe counting and accurate phase calculation even when 70% of optical specular reflectivity is lost due to surface grain faceting.

Read a polysilicon etch process IEP endpoint algorithm through a *dielectric-preservation-governor* lens: it is the metrology mechanism that allows an etch tool to sprint through the bulk of a thick polysilicon gate at maximum speed, and then brake smoothly nanometers above a fragile 1.2 nm gate oxide, guaranteeing electrical gate oxide integrity across billions of integrated transistors.

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