euv

Every transistor on an advanced chip starts as a pattern projected onto the wafer by a lithography machine. For decades that machine used deep-ultraviolet light at 193 nanometers, and as features shrank below what 193 nm could resolve, fabs kept up only by exposing each layer several times through multiple masks — slow, expensive multi-patterning. Extreme ultraviolet lithography breaks that logjam by switching to a wavelength roughly fourteen times shorter, and it is the single most concentrated chokepoint in the entire AI-chip supply chain.\n\n**What EUV is.** EUV lithography patterns the wafer with 13.5-nanometer light — extreme ultraviolet, on the edge of soft X-rays. That short wavelength resolves features far smaller than DUV can, which is what makes 7nm, 5nm, 3nm, and 2nm-class logic possible. Crucially, it lets a critical layer be printed in a single exposure where DUV would have needed four or more, cutting steps and improving yield.\n\n**Why it is so hard.** 13.5 nm light is absorbed by essentially everything — air, and ordinary glass lenses included. So an EUV scanner cannot use lenses at all: it uses reflective molybdenum-silicon multilayer mirrors, operating in a vacuum. Each mirror reflects only about 70 percent of the light, and the beam bounces off roughly ten of them before reaching the wafer, so most of the light is lost along the way. To compensate, the source has to be blindingly bright: a high-power CO2 laser vaporizes tens of thousands of tiny tin droplets per second into a plasma near 500,000 kelvin, and that plasma is what emits the 13.5 nm light.\n\n```svg\n\n```\n\n**Standard NA and High-NA.** Resolution scales with the numerical aperture of the optics. Today's production EUV tools (ASML's NXE line) run at 0.33 NA and resolve down to roughly 13 nm. The next step, High-NA EUV, raises that to 0.55 NA for about 8 nm resolution — but reaching it meant replacing every mirror in the projection column with larger, more steeply curved, more precisely figured reflectors and adopting anamorphic optics that image half a field at a time. The tool, ASML's TWINSCAN EXE:5200, costs on the order of 400 million dollars each.\n\n| Generation | Wavelength / NA | Resolution | Note |\n|---|---|---|---|\n| DUV | 193 nm | ~38 nm+ | Multi-patterning below its limit |\n| EUV (NXE) | 13.5 nm, 0.33 NA | ~13 nm | Single-exposure critical layers |\n| High-NA EUV (EXE) | 13.5 nm, 0.55 NA | ~8 nm | Anamorphic, half-field, ~$400M |\n\n**Who has it.** ASML in the Netherlands is the only company on earth that makes EUV scanners — a genuine single point of control, which is why EUV sits at the center of semiconductor export policy. On High-NA, Intel installed the industry's first commercial EXE:5200B tool for its 14A process, with Samsung and SK hynix also moving ahead, while TSMC has judged High-NA too costly for now and plans to hold standard-NA EUV longer before adopting it around its A14 generation. High-volume High-NA manufacturing is expected to ramp in 2027 to 2028.\n\n**Read through a quant lens rather than an optics lens,** and EUV is the hardest supply constraint to route around in all of computing: a single vendor, export-controlled, with multi-year lead times and nine-figure tool prices. Whether a fab has EUV — and eventually High-NA EUV — largely determines whether it can build competitive AI logic at all, which makes ASML's order book and shipment cadence a leading indicator for the entire leading edge. How the tin-plasma source power gates wafer throughput, why High-NA's half-field imaging forces design changes, and how EUV pellicles and mask defects bound yield are the natural next layers to go deeper on.