extreme ultraviolet lithography EUV

**Extreme Ultraviolet (EUV) Lithography** is **the advanced patterning technology using 13.5 nm wavelength light to print semiconductor features below 7 nm — replacing multiple patterning with single-exposure capability and enabling continued Moore's Law scaling through high-NA optics that achieve sub-8 nm resolution**. **EUV Source Technology:** - **Laser-Produced Plasma (LPP)**: high-power CO₂ laser (>20 kW) strikes tin (Sn) droplets at 50 kHz repetition rate; tin plasma emits 13.5 nm radiation; source power >250W at intermediate focus achieved in production (ASML NXE:3600D) - **Collection Efficiency**: multilayer Mo/Si collector mirror captures ~5% of emitted EUV photons; 40-pair Mo/Si stack with ~70% peak reflectivity at 13.5 nm; collector lifetime >30,000 hours with debris mitigation - **Dose and Throughput**: production dose ~30-60 mJ/cm² for chemically amplified resists; throughput >160 wafers per hour (wph) at 300 mm; higher source power directly increases throughput - **Hydrogen Buffer Gas**: low-pressure hydrogen protects optics from tin contamination; hydrogen radicals etch deposited tin; maintains mirror reflectivity over extended operation **Optical System:** - **All-Reflective Optics**: EUV absorbed by all materials; optical path uses 6 multilayer mirrors (NXE) or 8 mirrors (high-NA EXE); each mirror ~68% reflective; total optical transmission ~2-4% - **Numerical Aperture**: current NXE systems NA=0.33 with ~13 nm resolution (k1=0.31); high-NA EXE:5000 achieves NA=0.55 with ~8 nm resolution; anamorphic optics use 4×/8× demagnification - **Wavefront Control**: mirror figure accuracy <50 pm RMS; active mirror correction compensates thermal distortion during exposure; interferometric alignment maintains overlay <1.5 nm - **Flare and Stray Light**: scattered light from mirror roughness creates background exposure; flare <3% achieved through super-polished substrates with <0.1 nm RMS roughness **Mask Technology:** - **Reflective Mask**: 40-pair Mo/Si multilayer on ultra-low thermal expansion (ULE) glass substrate; absorber pattern (TaBN or alternative) defines circuit features; 4× magnification (features on mask 4× larger than on wafer) - **Pellicle**: thin membrane protecting mask from particles; EUV-transparent pellicle (polysilicon or CNT-based) must survive >80 W/cm² EUV irradiation; pellicle transmission >90% required to maintain throughput - **Mask Defects**: buried defects in multilayer are uniquely challenging; actinic (at-wavelength) inspection required to detect phase defects invisible to optical inspection; defect-free mask fabrication remains a yield limiter - **Mask 3D Effects**: finite absorber thickness creates shadowing effects dependent on feature orientation; computational lithography compensates through mask bias and OPC adjustments **Manufacturing Impact:** - **Single Patterning**: EUV replaces quad-patterning SADP/SAQP at critical metal and via layers; reduces process steps from 30+ to ~10 per layer; simplifies overlay budget and improves yield - **Node Adoption**: 7 nm (limited EUV), 5 nm (6-14 EUV layers), 3 nm (20+ EUV layers), 2 nm (high-NA EUV planned); TSMC, Samsung, Intel all deploying EUV in production - **Cost**: ASML NXE:3600D costs ~$200M per tool; high-NA EXE:5000 expected >$350M; EUV lithography cost ~$0.03-0.05 per cm² per layer; justified by reduced patterning complexity - **Stochastic Effects**: at sub-20 nm features, photon shot noise and resist chemistry randomness cause line edge roughness (LER) and local CD uniformity (LCDU) challenges; higher dose and improved resists mitigate EUV lithography is **the most complex and expensive manufacturing technology ever developed — its successful deployment at 13.5 nm wavelength has extended semiconductor scaling beyond what was thought physically possible, with high-NA EUV poised to enable chip manufacturing at the 2 nm node and beyond**.