extreme ultraviolet lithography euv
**High-NA EUV lithography** is the next-generation patterning system that increases the numerical aperture of the EUV projection optics from 0.33 to 0.55 — shrinking the minimum printable half-pitch from ~13 nm to ~8 nm in a single exposure. ASML's EXE:5000 (first shipment 2024, ~€350M per tool) is the only High-NA scanner; Intel is the lead customer (Intel 14A, ~2026), with TSMC and Samsung following. High-NA extends EUV lithography one or two more nodes beyond what current 0.33-NA systems can resolve, pushing the industry toward angstrom-scale patterning without falling back to costly multi-patterning.
**Resolution — Rayleigh's equation.** The minimum resolvable half-pitch (HP) in optical lithography:
$$\text{HP} = k_1 \cdot \frac{\lambda}{\text{NA}}$$
For current EUV ($\lambda$ = 13.5 nm, NA = 0.33, $k_1$ ≈ 0.3–0.4): HP ≈ 12–16 nm. For High-NA ($\lambda$ = 13.5 nm, NA = 0.55, $k_1$ ≈ 0.3–0.4): HP ≈ 7–10 nm. The 67% increase in NA delivers a proportional improvement in resolution — the same physics that drives microscope objectives, now at 13.5 nm wavelength with all-reflective optics in vacuum.
**Depth of focus — the trade-off.** Increasing NA narrows depth of focus (DoF):
$$\text{DoF} = k_2 \cdot \frac{\lambda}{\text{NA}^2}$$
At 0.55 NA: DoF drops by $(0.55/0.33)^2 \approx 2.8\times$ compared to 0.33 NA — from ~100 nm to ~35–45 nm. This razor-thin focus budget demands: (1) flatter wafers (global planarity <10 nm), (2) ultra-precise wafer stage leveling (real-time topography correction), (3) thinner resist stacks (~20–30 nm), and (4) tighter CMP uniformity across every underlayer.
**Anamorphic optics — the enabling innovation.** Simply scaling a 0.33-NA lens to 0.55 NA would require mirrors too large to manufacture. ASML's solution: an anamorphic (non-rotationally-symmetric) optical design that magnifies 4× in one axis and 8× in the perpendicular axis. This keeps mirror sizes manageable but means the mask field shrinks from 26×33 mm (standard EUV) to 26×16.5 mm in the scanning direction — exactly half the field area. Consequence: die sizes larger than 26×16.5 mm require field stitching (two exposures bonded at the overlap), which adds complexity and edge-placement error at the stitch boundary.
| Parameter | Current EUV (0.33 NA) | High-NA EUV (0.55 NA) | Impact |
|---|---|---|---|
| Numerical aperture | 0.33 | 0.55 | 67% higher resolution |
| Wavelength | 13.5 nm | 13.5 nm | Same EUV source |
| Min half-pitch (k₁=0.33) | ~13 nm | ~8 nm | Enables 14A / A14 nodes |
| Depth of focus | ~100 nm | ~35–45 nm | 2.8× tighter → thinner resist |
| Mask magnification | 4× (symmetric) | 4× × 8× (anamorphic) | Half field in scan direction |
| Exposure field | 26 × 33 mm | 26 × 16.5 mm | Large dies need stitching |
| Source power needed | 250–500 W | 500–800 W (target) | Higher dose demand |
| Resist thickness | 30–40 nm | 20–30 nm | Thinner → pattern collapse risk |
| Overlay budget | ~2 nm | <1.5 nm | Tighter stage/metrology |
| Throughput target | 150–200 WPH | 150+ WPH (goal) | Must match 0.33 NA economics |
| Tool cost | ~€180M (NXE:3800) | ~€350M (EXE:5000) | 2× cost → must print 2× more layers/tool |
**The half-field problem.** Because the exposure field is halved in one dimension, any chip larger than ~26×16.5 mm must be exposed in two stitched shots. For AI accelerators (H100 die = 814 mm², MI300X chiplet = ~700 mm²), this means either: (a) redesigning the chip to fit within the half-field (costly), (b) stitching with sub-1 nm overlay accuracy (challenging), or (c) using High-NA only for the most critical layers (metal/via pitches below ~20 nm) while keeping the rest on 0.33-NA EUV or immersion (the expected initial approach).
**Resist challenges.** Thinner resist (~20–25 nm) with reduced photon shot noise requires higher EUV dose — but EUV source power is finite, so throughput degrades without mitigation. Metal-oxide resists (MOx, e.g. tin-oxide-based inorganic resists) offer 2–3× better EUV absorption than chemically-amplified resists (CAR) at the same thickness, enabling adequate dose at production throughput. Dry-development resists (no wet puddle) reduce pattern collapse in the high-aspect-ratio features that thin resist creates.
**Source power.** Current EUV sources deliver 250–500 W of in-band 13.5 nm power to the intermediate focus. High-NA needs 500–800 W to maintain throughput at the higher dose demanded by thinner resist and finer features. ASML/Trumpf's tin-droplet laser-produced-plasma (LPP) source is being scaled with higher-repetition-rate CO₂ lasers (~100 kHz) and optimized tin-droplet targeting. Reaching 800 W in-band is the critical path item for High-NA productivity parity with 0.33-NA tools.
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**Economics — the $350M question.** A single EXE:5000 costs roughly €350M — nearly twice the NXE:3800 (€180M). To justify the investment, each High-NA tool must process enough wafers at enough layers to amortize its cost over production volume. Intel's calculus: High-NA eliminates the need for EUV double-patterning (which uses two 0.33-NA exposures per layer), so one High-NA shot replaces two 0.33-NA shots at critical metal layers — effectively doubling the throughput per critical layer and justifying the tool premium. The break-even requires High-NA throughput to reach at least 150 WPH (wafers per hour) at production dose.
**What High-NA means for AI chip manufacturing.** The tightest metal pitches on next-generation AI accelerators (18–20 nm M1 pitch at Intel 14A / TSMC A14) are below what 0.33-NA EUV can resolve in a single exposure. Without High-NA, these layers would require EUV double-patterning — doubling litho cost and halving effective throughput at the most expensive process step. High-NA makes single-exposure patterning at 8–10 nm half-pitch practical, keeping Moore's Law cost scaling alive for the transistor-dense accelerator dies that power frontier AI training.