Confront Resistor Transistor Logic Fan Out and Noise Margin Limits

# Confront RTLs Fan-Out and Noise-Margin Limits

## 1. Why RTL's Noise Margin Was the Family's Actual Practical Ceiling

Measured across real RTL gates driving real fan-out loads, the noise margin between a guaranteed logic '1' and a guaranteed logic '0' narrows steadily as fan-out count rises, until at some fan-out limit — typically a handful of loads for a standard RTL gate — the margin becomes too thin to guarantee reliably across manufacturing variation and temperature, setting a hard, practical ceiling on how large an RTL-based system could be built before errors crept in. This is a quantitative, not qualitative, limit:

## 2. Real Diagram: Why This Specific Weakness Pointed Directly at Diode-Transistor Logic

Diode-transistor logic's one structural change — replacing RTL's input resistors with input diodes — does not touch the switching device at all; it changes only how the logic-'0' input level is clamped, which is precisely the mechanism responsible for RTL's fan-out-dependent margin erosion. This is why Step 10 presents DTL as a targeted fix to this exact measured problem, not an unrelated alternative family.

## 3. Why This Specific Weakness Pointed Directly at Diode-Transistor Logic

Nothing about the underlying bipolar transistor changes between RTL and DTL — the fix is purely in how the input network presents a logic level to that transistor's base, a distinction worth keeping clear before Step 10 covers DTL itself.