Characterize Yield Limits That Kept Experimental Mos Out of Production Volume

# Characterize Yield: Why Experimental MOS Struggled to Reach Production Volume

## 1. Why Laboratory Success Did Not Translate Directly Into a Shippable Product Line

Across RCA's, Fairchild's, and the other contemporaneous MOS development programs, functioning demonstration devices and even small demonstration circuits were reproducibly achievable by the early-to-mid 1960s, but die yield at any chip size large enough to be commercially useful remained low, driven primarily by the combination of threshold-voltage scatter (Step 4), unresolved contamination risk even after the PSG fix (Step 14) was only partially adopted across the industry at this point, and gate-oxide pinhole defects that a planar bipolar process's thicker, less electrically critical oxide layers tolerated far better. The yield-limiting defect sources, measured and ranked:

## 2. Real Diagram: Yield Versus Die Area, the Curve That Actually Set the Production Ceiling

Because defect density per unit area stayed roughly constant across process batches in this era, yield fell steeply as die area increased — directly undercutting the density advantage Step 15 showed on paper, since realizing that advantage required building larger die than this era's gate-oxide defect rate could reliably support.

## 3. Yield Versus Die Area, the Curve That Actually Set the Production Ceiling

This is the manufacturing reality that kept experimental MOS experimental through the mid-1960s: the device physics worked, the circuit concept worked, and the density/power case was real, but the specific process discipline needed to yield that case at commercial die sizes had not yet caught up — a gap the industry would close later in the decade, outside this series' own chronological scope.