Scale Experimental Mos Gate Density Against Bipolar Rtl and Dtl Gate Density
# Scale Experimental MOS Gate Density Against Bipolar RTL and DTL Gate Density
## 1. Why a Single MOS Transistor Could Replace Several Bipolar Components Per Gate
An RTL or DTL NOR gate requires one bipolar transistor plus two or more discrete resistors (or diodes) per gate, each consuming its own chip area, while a comparable MOS NOR gate can be built from MOS transistors alone, with the pull-up function itself implemented as another MOS transistor rather than a separate resistor — fewer distinct component types per logic function, and therefore a real area-density advantage that compounds as gate count rises. The per-gate component count, counted directly:
## 2. Real Diagram: Why This Density Advantage Still Could Not Be Fully Realized in 1962-1965
The component-count advantage shown above was real and measurable, but Step 18's yield data shows experimental MOS processes of this era could not yet translate it into actual shipped gate density, because defect density per unit area was still high enough that larger MOS die (needed to realize the density advantage at scale) failed at unacceptable rates — the advantage existed on paper years before manufacturing caught up enough to deliver it as product.
## 3. Why This Density Advantage Still Could Not Be Fully Realized in 1962-1965
Keeping these two findings distinct — a real per-gate density advantage, against a real, separate manufacturing limitation preventing its delivery — is the honest way to read this era's MOS story, rather than either overstating MOS's immediate competitiveness or dismissing its eventual trajectory.