Bipolar Ecl 1960s Confront the Dtl Rtl Speed Ceiling
# Bipolar ECL Logic (1960s): Step 1 — Confronting the DTL/RTL Speed Ceiling
Why resistor-transistor and diode-transistor logic ran out of road by the early 1960s. RTL (resistor-transistor logic) and DTL (diode-transistor logic) built the first practical bipolar digital logic families, and both shared one structural habit that limited them: the switching transistor was driven hard into saturation on every '0'-to-'1' transition, and pulled back out of saturation on every '1'-to-'0' transition. Saturated bipolar operation gives excellent noise immunity and simple biasing, but it stores excess minority carriers in the base that must be swept out before the transistor can turn off — a delay with no useful work attached to it. Step 1 frames the problem the rest of this 20-step series on Emitter-Coupled Logic (ECL) solves: a logic family that never lets its transistors saturate in the first place, trading some of RTL/DTL's simplicity and noise margin for a decisive and lasting speed advantage. This series picks up the bipolar transistor technology already covered in the point-contact, alloy-junction, and grown-junction series — ECL's speed came from circuit topology, not from a new transistor process.
## 1. What Saturation Costs a Logic Gate
When a bipolar transistor is driven into saturation, both its base-emitter and base-collector junctions are forward biased, and the base region fills with excess minority carriers well beyond what active-region operation requires. Turning the transistor off again is not simply a matter of removing base drive — the stored charge must first recombine or be extracted, a process called storage-time delay (t_s), and in 1960s epitaxial planar bipolar transistors storage time routinely ran 10-30 nanoseconds, dwarfing the few-nanosecond active-region delays of the same device. RTL and DTL gates, built from these transistors switched to saturation, inherited that storage-time tax on every gate in a chain. A counter or shift register built from cascaded RTL/DTL stages accumulated storage-time delay stage after stage, and by the early 1960s this was the dominant limit on how fast a computer's logic could run — not transistor intrinsic speed, but the time spent recovering from deliberately saturating every gate.
## 2. Why the Obvious Fixes Fell Short
## 3. Companion Diagram: Stage Sequence and Trend Summary
## Confronting the DTL/RTL Speed Ceiling's Place in the Process Lineage
This is step 1 of 20 in the Bipolar ECL Logic (1960s) series, tracing the move from saturated switching to the non-saturating differential-pair topology that let ECL dominate the fastest digital logic from the mid-1960s through the 1980s.