Bipolar Ecl 1960s Confront the Power Dissipation Tradeoff
# Bipolar ECL Logic (1960s): Step 11 — Confronting the Power Dissipation Tradeoff
ECL's other defining characteristic, and the main reason it never displaced TTL for general-purpose logic. Step 2 noted in passing that a current switch draws roughly the same supply current whether its output is a '1' or a '0', because current is steered rather than turned on and off. This step works out the consequence of that property at the scale of a real digital system, and explains why 'ECL is power-hungry' became a lasting, accurate reputation rather than an exaggeration.
## 1. Why ECL Power Is State-Independent
A saturating-logic gate (RTL, DTL, TTL) draws significant current primarily while switching and comparatively little while sitting in a steady '0' or steady '1' state, so its average power scales roughly with switching activity — a mostly-idle circuit draws much less power than a continuously-toggling one. An ECL current switch, by design, always has its full bias current flowing through one side of the differential pair or the other; it is never 'off' in the sense of drawing negligible current. A typical first-generation MECL gate drew on the order of 1.5-3 milliwatts of static power per gate continuously, roughly five to ten times a comparable TTL gate's average power at modest switching rates, and that multiple only grows more favorable to ECL as switching frequency rises, because TTL's switching-dependent power climbs with frequency while ECL's static power does not change much with frequency at all.
## 2. Real Diagram: Power vs. Clock Frequency, ECL vs. TTL
## 3. The System-Level Consequence: Heat, Not Just Watts
A board populated densely with ECL logic concentrates continuous power dissipation in a small area regardless of how much useful switching is happening, which 1960s mainframe designers had to address with forced-air cooling, close component spacing limits, and in some cases (famously, later Cray systems) liquid cooling — a thermal-design burden examined directly in Step 18. This is the central tradeoff of the whole ECL story: the same non-saturating current-switch topology that eliminates storage-time delay (Steps 1-3) also guarantees that power draw cannot be reduced simply by switching less often, which is exactly why ECL stayed a specialist's tool for the highest-performance subsystems rather than becoming the default logic family the way TTL did, and later why CMOS's near-zero static power eventually displaced ECL even in those specialist roles (Step 20).
## 4. Companion Diagram: Stage Sequence and Trend Summary
## Confronting the Power Dissipation Tradeoff's Place in the Process Lineage
This is step 11 of 20 in the Bipolar ECL Logic (1960s) series, establishing why ECL's non-saturating speed advantage comes bundled with state-independent, continuously high power draw.