Bipolar Ecl 1960s Adopt the Differential Pair Current Switch
# Bipolar ECL Logic (1960s): Step 2 — Adopting the Differential-Pair Current-Switch Topology
The circuit idea at the heart of every ECL gate. Instead of a single switching transistor that is driven fully on or fully off, ECL's basic cell is a differential pair: two transistors sharing a common emitter resistor (or current source), with one base driven by the input signal and the other held at a fixed reference voltage, V_BB. A constant total current flows through the pair, and the circuit's only job is to decide which of the two transistors carries that current — it never turns either transistor fully off and never drives either one into saturation. This 'current switch' or 'current steering' topology is the mechanism that makes everything else in this series possible: non-saturating operation, well-defined logic levels, high fan-out, and sub-nanosecond propagation delay all trace back to this one circuit choice.
## 1. How the Current Switch Decides
With both transistor bases near the same voltage and a shared emitter node, the pair behaves like a voltage comparator riding on a fixed current budget: whichever base sits higher steals essentially all of the shared emitter current, while the other transistor's emitter-base junction becomes slightly reverse-biased and its collector current drops toward zero. Because the total current is fixed by the emitter resistor/current source and the supply rails, neither transistor's collector voltage ever swings low enough to forward-bias its collector-base junction — the condition that defines saturation. The input only needs to differ from V_BB by a few hundred millivolts (roughly four times the thermal voltage kT/q) before the current switch is essentially fully committed to one side, so small voltage swings are enough to produce a clean digital decision.
## 2. Real Diagram: The Current-Switch Core
## 3. Consequences That Flow From This One Choice
Because both transistors stay in the active region at all times, there is no storage-time delay to recover from on any transition — switching speed becomes limited by transistor transit time and node capacitance charging, not by minority-carrier recombination. Because the current is steered rather than switched on and off, the power supply current drawn by the gate is nearly constant regardless of logic state, which simplifies power-supply design but also means ECL draws roughly the same current whether it is doing useful work or sitting idle — the origin of ECL's power-hungry reputation, taken up in Step 11. Step 3 looks more closely at why this topology is specifically non-saturating, and Step 4 adds the output stage that turns the current-switch collector voltages into usable logic signals.
## 4. Companion Diagram: Stage Sequence and Trend Summary
## Adopting the Differential-Pair Current-Switch Topology's Place in the Process Lineage
This is step 2 of 20 in the Bipolar ECL Logic (1960s) series. The differential-pair current switch introduced here is the circuit core that every later step in this series builds on or explains the consequences of.