Bipolar Ecl 1960s Define Current Mode Logic Levels
# Bipolar ECL Logic (1960s): Step 5 — Defining Current-Mode Logic Levels
Why ECL's '1' is a small negative voltage and its '0' is a slightly more negative voltage — and why that is a deliberate, not incidental, choice. Most logic families of the era (RTL, DTL, and soon TTL) used positive logic swings referenced to a 0 V ground rail, with '1' the higher voltage. ECL inverts this convention: the standard family (which becomes MECL, covered in Step 15) runs from a 0 V ground rail and a negative supply, typically -5.2 V, with logic '1' near -0.8 V and logic '0' near -1.6 V — both negative, both close to ground, separated by roughly 0.8 V. This step explains the electrical reasoning behind that choice.
## 1. Why Negative Supply, Ground-Referenced Output
Putting the positive rail at ground and the negative rail at -5.2 V (rather than, say, 0 V and +5.2 V) keeps the transistor collectors, which connect toward the positive rail through the collector resistors, near ground potential rather than near the full supply magnitude. This matters because stray capacitance to the grounded chassis and PCB ground plane then sees a signal that swings only a few hundred millivolts relative to a stable, low-noise reference, rather than swinging relative to a rail that itself may carry supply noise. It also means the output stage's emitter followers, which sit one diode drop below their collector-switch inputs, land naturally in the -0.8 V to -1.6 V range without needing an additional level-shifting stage. The cost is that ECL cannot share a single positive 5 V supply rail with contemporary TTL without an interface circuit — a practical nuisance that shows up repeatedly in mixed-logic mainframe backplanes of the era (touched on again in Step 19).
## 2. Real Diagram: ECL vs. TTL Logic-Level Voltage Map
## 3. The ~0.8 V Swing Is a Design Choice, Not a Minimum
The roughly 800 mV separation between logic '1' and logic '0' is set by the current switch's emitter resistor and current source sizing, not by any physical floor — it is chosen to be several times the diode-equation thermal term (kT/q, about 26 mV at room temperature) so that the current switch fully commits current to one side with comfortable margin, while staying as small as practical to minimize the time spent charging node capacitance through that swing. A larger swing would improve noise margin modestly but cost propagation delay proportionally, since delay scales with the voltage swing that has to be slewed through a given drive current and capacitance — exactly the tradeoff explored quantitatively in Step 9's propagation-delay analysis.
## 4. Companion Diagram: Stage Sequence and Trend Summary
## Defining Current-Mode Logic Levels's Place in the Process Lineage
This is step 5 of 20 in the Bipolar ECL Logic (1960s) series, defining the negative, ground-referenced logic levels that distinguish ECL from every positive-logic bipolar family of the same era.