fault coverage

Fault coverage is the percentage of possible manufacturing defects that can be detected by a given test program, measuring test quality and the ability to screen defective chips. Definition: Fault Coverage = (Detected faults / Total possible faults) × 100%. Fault models: (1) Stuck-at—node permanently at 0 or 1 (most basic model); (2) Transition—node slow to transition (detects timing-related defects); (3) Path delay—cumulative delay through specific paths; (4) Bridging—unintended short between adjacent signals; (5) IDDQ—elevated quiescent current from defect-induced leakage; (6) Cell-aware—faults within standard cell internals. Fault coverage targets: (1) Consumer—95-98% stuck-at; (2) Automotive—99.5%+ stuck-at, 95%+ transition; (3) Aerospace/medical—99.9%+ with multiple fault models. ATPG (Automatic Test Pattern Generation): tools generate test vectors to detect faults—Synopsys TetraMAX, Cadence Modus, Mentor Tessent. Coverage metrics: (1) Stuck-at fault coverage—percentage of detectable stuck-at faults; (2) Transition fault coverage—timing-related fault detection; (3) Test coverage—includes all fault types; (4) DPPM prediction—estimated defective parts per million escaping to customer. Improving fault coverage: (1) DFT—scan chains (convert sequential to combinational), BIST, compression; (2) ATPG optimization—more patterns, better fault targeting; (3) Multi-fault model—combine stuck-at + transition + bridging; (4) IDDQ testing—catches defects invisible to structural tests. Diminishing returns: going from 95% to 99% coverage may require 3× more test patterns and time. Fault coverage directly correlates with outgoing quality—higher coverage means fewer defective chips reach customers, critical for zero-defect automotive and safety applications.