filler cell

**Physical-Only Cells (Filler, Decap, Tap)** are **non-functional standard cells placed during physical design to satisfy process requirements, improve power integrity, and close layout design rules** — invisible to logic simulation but essential for chip manufacturability. **Filler Cell** - **Purpose**: Fill empty gaps in standard cell rows between functional cells. - **Contains**: N-well tie, substrate tie, VDD/VSS rails — no logic. - **Required for**: Continuous N-well implant across row (prevents well doping discontinuity → Vt variation). - **DRC**: Without fillers, gaps create N-well/P-well spacing violations. - **Varieties**: Full-width and fractional-width fillers (1-site, 2-site, etc.) to fill all gaps exactly. **Decoupling Capacitance (Decap) Cell** - **Purpose**: Add on-chip capacitance between VDD and VSS to suppress power supply noise. - **Contains**: Large MOSFET with gate tied to VDD and source/drain tied to VSS (acts as MOS capacitor). - **Mechanism**: When switching transient creates IR drop on VDD, decap capacitor releases stored charge → maintains local supply voltage. - **Placement**: Near high-switching cells (clock gating cells, wide muxes, output drivers). - **Leakage concern**: Decap cells consume static leakage — over-insertion increases power consumption. - **Tradeoff**: Power noise reduction vs. leakage power increase. **Tap Cell (Well Tap Cell)** - **Purpose**: Connect N-well to VDD and P-substrate to VSS at regular intervals. - **Required**: Floating well/substrate → latch-up susceptibility and Vt drift. - **Pitch**: Placed every 30–60 standard cell heights in each row (per foundry rule). - **EndCap cells**: Special tap cells placed at row ends — required by foundry for N-well termination. **Tie Cell (Tie-Hi, Tie-Lo)** - **Purpose**: Connect constant logic 0 or 1 to cell inputs that must be fixed. - **Why not VDD/VSS directly**: DRC prohibits direct connection of VDD to gate input in advanced nodes (antenna risk, latch-up risk). - **Contains**: PMOS tied to VDD (tie-hi) or NMOS tied to VSS (tie-lo) → outputs clean logic level. Physical-only cells are **silent enablers of DRC-clean, manufacturable layouts** — a chip with missing fillers, insufficient decap, or improperly spaced tap cells will fail DRC signoff or exhibit reliability and performance issues in silicon.