finfet

FinFET is the 3D transistor that carried the industry from 22 nm down to 3 nm: the channel is a thin vertical silicon fin, and the gate wraps over three of its sides instead of sitting on one flat face.\n\n**It exists to stop leakage.** As planar transistors shrank, the gate — touching the channel on only its top face — lost electrostatic grip, and current leaked even when the device was supposed to be off, wasting power. Standing the channel up as a fin and wrapping the gate around three sides restores control: the gate can shut the channel off cleanly at far shorter lengths.\n\n**Drive current comes from fin count, not fin width.** A single fin carries limited current, so designers place several fins in parallel under one gate. The conducting surface is the fin's height times its two sidewalls plus its top, so taller fins and more fins mean more drive — current scales in quantized steps of whole fins, which is why FinFET layouts are drawn in integer fin counts rather than smooth transistor widths.\n\n| Attribute | Planar | FinFET | GAA nanosheet |\n|---|---|---|---|\n| Gate control | 1 face (top) | 3 faces | 4 faces (all around) |\n| Channel shape | flat surface | vertical fin | stacked sheets |\n| Node range | >= 28 nm | 22 nm - 3 nm | 2 nm and below |\n| Drive tuning | width (analog) | fin count (quantized) | sheet width (analog) |\n| Off-state leakage | high at short L | much lower | lowest |\n\n```svg\n\n```\n\n**FinFET is the bridge, not the destination.** Intel's 22 nm Tri-Gate (2011) and TSMC's 16 nm brought it to volume, and it dominated the 16 / 14 / 10 / 7 / 5 / 3 nm generations. But even a three-sided gate eventually loses control, so at 2 nm the leading fabs move to gate-all-around nanosheets, where the gate surrounds the channel on all four sides.\n\nRead FinFET through a quant lens rather than a diagram lens: what you are buying is electrostatic control — a subthreshold slope closer to the 60 mV/decade ideal, lower off-current, and drive current quantized in whole fins. Those parameters set the power-performance curve a design can reach at a given node, which is the number that actually shows up as a chip's energy per operation.