fpga prototyping

**FPGA Prototyping / Emulation** — mapping a chip design onto FPGAs to verify functionality at near-real speed, enabling early software development before silicon is available. **Why Emulation?** - RTL simulation: ~1-100 Hz (too slow for running an OS or real workloads) - FPGA emulation: ~1-10 MHz (1000x+ faster — can boot Linux, run software stacks) - Silicon speed: ~1-5 GHz (final product) **Approaches** - **FPGA Prototyping**: Map design to commercial FPGA boards (Xilinx/Intel). Cheaper, less automation - **Emulation Systems**: Dedicated platforms with many FPGAs + automation. Much faster compile, better debug - Synopsys ZeBu - Cadence Palladium (up to 20B gates) - Siemens Veloce **Use Cases** - Boot operating system months before silicon - Hardware/software co-verification - Performance validation with real workloads - Driver and firmware development - System-level validation with real peripherals **Limitations** - FPGA logic is 10-100x larger than ASIC — may need many FPGAs for a large chip - Timing is not representative (FPGA routing delays differ from ASIC) - Some analog/mixed-signal blocks can't be emulated **Emulation** is essential for the modern chip development cycle — it de-risks silicon bringing and accelerates time-to-market.