From Sands to Silicon
From sands to silicon is the industrial sequence that turns ordinary quartz sand into a mirror-flat single crystal pure enough to build transistors on. It spans roughly nine orders of magnitude of purification and a complete change of atomic order, in about a dozen steps. The input is silicon dioxide — the second most abundant compound in the Earth's crust, worth a few cents per kilogram. The output is a 300 mm prime wafer: one continuous crystal with fewer than one stray atom in ten billion, flat to a few tens of nanometres across an area the size of a dinner plate, and worth well over a hundred dollars before a single transistor is patterned on it.
The chain exists because silicon must satisfy three requirements that no single process delivers at once. It must be the right element, so the oxygen has to go. It must be almost unimaginably pure, because a metal atom in the channel is a recombination centre and a lifetime killer. And it must be one crystal, because grain boundaries scatter carriers and pin dopants. Reduction, purification and crystallisation are three different problems, solved in that order by three different technologies.
Carbothermic reduction turns sand into silicon, but not into pure silicon. Quartz is fed with a carbon source — coke, charcoal, wood chips — into a submerged-arc furnace and held near 1900 °C, where SiO₂ + 2C → Si + 2CO. The carbon strips the oxygen and leaves molten metallurgical-grade silicon, tapped off at 98–99% purity and called 2N. This is a commodity: several million tonnes a year, most of it destined for aluminium alloys and silicones rather than chips. As the chart above shows, the step buys almost nothing in purity. Iron, aluminium, calcium, boron and phosphorus all follow the silicon straight through, and boron and phosphorus are the two that matter most, because they are the dopants themselves and no later step removes them easily.
The Siemens process does the real purification, and it does it by turning the solid into a gas. You cannot filter atoms out of a lump of metal, so MG-Si is converted into something that can be distilled. Ground silicon reacts with hydrogen chloride near 300 °C to give trichlorosilane, SiHCl₃, a liquid boiling at 31.8 °C. Fractional distillation then does what no solid-state process can: it separates on boiling point, repeatedly, until the metal chlorides are gone. The purified trichlorosilane is decomposed back onto electrically heated silicon rods at roughly 1100 °C, growing them over several days into polysilicon of 9N to 11N purity — 99.9999999% and better. This step dominates the energy budget of the whole chain, which is why fluidized-bed reactors producing granular polysilicon at a fraction of the power keep taking share, trading some purity for a great deal of electricity.
Czochralski pulling is what converts pure-but-random polysilicon into a single crystal. The polysilicon is melted in a fused-silica crucible at 1414 °C, an oriented seed crystal is dipped into the surface, and the seed is withdrawn while both seed and crucible rotate. The first thing the operator does is deliberately make the crystal too thin: the Dash neck, pulled fast down to about 3 mm, gives dislocations a short path to the free surface where they terminate. Only once the crystal is dislocation-free does it get shouldered out to full diameter. A 300 mm ingot runs 1 to 2 metres and 200 to 450 kg. Dopant added to the melt sets resistivity, and oxygen dissolved from the crucible wall at 10–20 ppma is not contamination but a design parameter: it precipitates during later thermal steps into internal gettering sites that trap metals away from the device layer, and it pins dislocations so the wafer resists thermal slip.
Float-zone growth exists because the crucible is the problem. Holding molten silicon in fused silica guarantees oxygen contamination, so float zone dispenses with the container entirely: a polysilicon rod is held vertically and a radio-frequency coil sweeps a molten zone along it, held by surface tension alone. Nothing touches the melt, so oxygen and carbon fall two to three orders of magnitude and resistivity can reach thousands of ohm-centimetres. The price is diameter and cost. Float-zone silicon goes into power devices, radiation detectors and high-voltage rectifiers; essentially all logic and memory is Czochralski, oxygen and all.
Wafering is the step where most of the crystal is thrown away. The ingot is cropped, ground to an exact diameter and notched for orientation, then a diamond-impregnated wire finer than a human hair saws hundreds of wafers at once. Kerf loss and the grinding before it consume a large fraction of a crystal that took days and a great deal of electricity to grow, and every wafer emerges with saw damage several microns deep that all subsequent shaping exists to remove.
| Stage | Input | Output | Typical temperature | What it actually controls |
|---|---|---|---|---|
| Carbothermic reduction | Quartz + carbon | MG-Si, 2N | 1900 °C | Removes oxygen, not impurities |
| Chlorination | MG-Si + HCl | Trichlorosilane | 300 °C | Makes purity a distillation problem |
| Fractional distillation | Crude SiHCl₃ | SiHCl₃, ~9N | 32 °C | Strips metal chlorides |
| Siemens CVD | SiHCl₃ + H₂ | Polysilicon, 11N | 1100 °C | Sets the electronic purity floor |
| Czochralski pull | Polysilicon | Single-crystal ingot | 1414 °C | Crystallinity, resistivity, oxygen |
| Wire sawing | Ingot | As-cut wafers | ambient | Thickness, bow, kerf yield |
| Lap, etch, CMP | As-cut wafers | Polished wafers | ambient–80 °C | Flatness, damage removal |
| Epitaxy | Polished wafers | Epi wafers | 1100 °C | Device-layer perfection |
Shaping and polishing exist to undo the saw. Lapping with an alumina or silicon-carbide slurry flattens the wafer and removes the worst damage; the edge is profiled to a rounded contour so it cannot chip and seed dislocations; an alkaline or acid etch then strips the remaining work-damaged layer chemically, leaving no new damage behind. Chemical-mechanical polishing then finishes the job, a colloidal-silica slurry at high pH performing a simultaneous chemical attack and mechanical abrasion that leaves a surface with sub-nanometre roughness. Double-side polishing controls flatness; a final single-side polish delivers the device surface. What the fab buys is then specified not as purity but as geometry: site flatness in tens of nanometres, nanotopography, total thickness variation, and a counted, sized population of light-point defects.
Epitaxy is optional, and most advanced logic buys it anyway. A thin single-crystal layer is grown on the polished surface by chemical vapour deposition at around 1100 °C, taking its orientation from the substrate beneath. The epi layer is grown, not pulled, so it carries no crystal-originated particles, takes its own doping, and can sit on a heavily doped substrate that suppresses CMOS latch-up. The wafer underneath does the mechanical and gettering work; the few microns on top do the electrical work.
The economics explain why this is a business with four significant suppliers rather than four hundred. Sand is free, metallurgical silicon is a commodity, and the Siemens step is an electricity trade. Czochralski growth is a slow, capital-intensive art in which one dislocation ruins a crystal worth tens of thousands of dollars, and wafer finishing is a metrology business measured in nanometres. Nearly all the value, and nearly all the risk, sits in the last three steps.
The wafer is not the product. It is the substrate on which several hundred further process steps will be performed, and its only job is to be good enough that none of them can blame it.