Full-Adder

A full adder is a digital circuit that adds three single-bit inputs together — two data bits plus an incoming carry bit from a lower bit position — producing a sum bit and a carry-out bit, built internally from two half adders plus an extra OR gate combining their carry outputs. That third input, the carry-in, is exactly what a half adder lacks and exactly what makes a full adder the building block that actually scales: chain enough full adders together, one per bit position, and the result is a complete circuit capable of adding binary numbers of any width a chip's arithmetic logic unit needs. How a full adder actually combines three input bits into a sum and a carry-out looks like this:

A few things are worth knowing about why accepting a carry-in is the one change that turns a limited building block into a fully scalable one:

A full adder's internal structure is literally two half adders wired together with one extra gate, which is exactly why half adders are taught first — a full adder isn't a separate design from scratch, it's the straightforward extension that fixes the one thing a half adder can't do. The first half adder adds the two primary data inputs together, producing an intermediate sum and an intermediate carry; the second half adder then adds that intermediate sum to the incoming carry-in bit, producing the final sum output along with a second intermediate carry. Because it's possible, though not guaranteed, for both of those intermediate carries to occur in the same addition, a single OR gate combines them into the final carry-out — if either half adder detected a carry condition, the full adder as a whole needs to carry out, which is exactly what OR's behavior captures.

Chaining a full adder's carry-out directly into the next bit position's carry-in is what builds a complete ripple-carry adder, a circuit that can add binary numbers of arbitrary width using nothing but a row of identical full adder cells — but that same ripple structure carries a real speed cost that grows with bit width. Each full adder in the chain can't finish computing its own sum until it knows whether a carry arrived from the position below it, so in the worst case — adding two numbers where a carry has to propagate all the way from the least significant bit to the most significant one — the total time the adder takes to produce a correct result grows in direct proportion to how many bits wide it is. For a narrow adder this delay is negligible, but for the wide adders inside a modern processor's arithmetic logic unit, handling 64-bit or wider numbers, that linearly growing worst-case delay becomes a real performance bottleneck that simple ripple-carry chaining alone can't avoid.

Carry-lookahead adders exist specifically to break that linear delay growth, computing the carry into every bit position directly and in parallel from the original input bits, rather than waiting for it to ripple through each stage in sequence. Instead of each full adder patiently waiting for the stage below it to resolve its carry, a carry-lookahead adder uses additional logic to compute, essentially simultaneously, what every bit position's carry-in will be, based directly on the original A and B inputs across the whole adder — trading a meaningfully larger and more complex circuit for a dramatically shorter worst-case delay that no longer scales linearly with bit width. This speed-for-complexity tradeoff is exactly why a processor's core arithmetic logic unit, where addition speed directly limits how fast the whole chip can execute instructions, almost always uses a carry-lookahead or similarly optimized adder architecture rather than a simple ripple-carry chain, despite the ripple-carry version being conceptually much easier to understand and build.

A full adder's role extends well beyond simple addition instructions, because binary subtraction, multiplication, and address calculation inside a processor all ultimately route through the same adder hardware rather than needing entirely separate circuits. Subtraction is typically implemented as addition of a negated number, using two's complement representation, which means a processor's existing adder circuitry handles subtraction too with only a small amount of extra control logic, not a whole separate subtractor circuit. Multiplication algorithms built from repeated shifting and adding, and the address calculations a processor performs constantly to locate data in memory, both lean on the same underlying adder hardware as their core computational engine — which is exactly why the humble full adder, chained and optimized into a fast, wide adder, sits at the functional center of far more of a processor's actual work than its simple name suggests.

Read a full adder as the full-adder-to-half-adder relationship, not a standalone design: its one added capability, accepting a carry-in, is precisely what lets identical copies of it chain together into an adder of any width, and the real engineering story from there is almost entirely about speed — ripple-carry simplicity traded for carry-lookahead performance — because this same chained adder hardware, reused for subtraction, multiplication, and address calculation, sits directly in the critical path of nearly everything a processor computes.