Half-Adder

A half adder is a digital circuit that adds two single-bit binary numbers together, producing two outputs: a sum bit and a carry bit, built from nothing more than one XOR gate and one AND gate wired to the same two inputs. The name "half" is deliberate and meaningful — this circuit can only add two bits together and has no way to accept an incoming carry from a previous, lower-order bit position, which is exactly the limitation a full adder exists to fix. Despite that limitation, a half adder is the conceptual starting point for every piece of binary addition hardware a chip contains, from the simplest counter to the arithmetic logic unit inside a processor core. How a half adder actually produces its sum and carry from two input bits looks like this:

A few things are worth knowing about why addition needs two separate outputs, and why a half adder's simplicity is also exactly its limitation:

Binary addition of two single bits can produce a result that doesn't fit in a single bit, which is the entire reason a half adder needs two separate outputs rather than one. Adding 1 and 1 in binary gives 10, a result that needs two bit positions to represent: a 0 in the current position and a 1 carried into the next position up, exactly mirroring how adding 5 and 5 in decimal gives 10, carrying a 1 into the tens place. The sum output captures the result bit that stays in the current position, while the separate carry output captures the overflow bit that has to be added into the next higher bit position — and because XOR naturally outputs 1 exactly when the inputs differ, while AND naturally outputs 1 exactly when both inputs are 1, these two simple gates happen to implement exactly those two separate pieces of binary addition's truth table without any extra logic needed.

A half adder's missing carry-in input is exactly what stops it from being chained together to add numbers wider than a single bit, and that gap is precisely what defines the difference between a half adder and a full adder. Adding two multi-bit binary numbers requires propagating a carry out of each bit position into the next higher position, the same way carrying works in ordinary decimal addition — but a half adder has no way to receive that incoming carry from the position below it, so wiring half adders together directly to add wider numbers simply doesn't work. A full adder solves this by adding a third input, a carry-in, built internally from two half adders plus an extra OR gate to combine their carry outputs, which is exactly why a half adder is usually introduced first: it's the simpler building block a full adder is constructed from, not a smaller, interchangeable alternative to it.

Despite being unable to chain for multi-bit addition on its own, a half adder's exact-match behavior makes it independently useful anywhere a circuit just needs to know whether two single bits are the same or different, not just for arithmetic. The XOR output alone, separate from any carry consideration, is 1 exactly when its two inputs differ and 0 when they match — a property reused directly in parity-checking circuits, simple comparators, and bit-difference detection logic throughout digital design, completely independent of whether binary addition is the actual goal. This is a common pattern in digital logic: a circuit built for one specific job, here single-bit addition, turns out to contain a smaller piece, the XOR gate's equality-testing behavior, that gets reused on its own in entirely unrelated contexts.

The least-significant bit position in any multi-bit adder is the one place in the entire chain where a half adder is both sufficient and the natural choice, because there's no lower bit position to carry in from in the first place. Every bit position above the least-significant one needs a full adder specifically because it must accept a carry-in from the position below it; the very first, lowest bit position has no position below it to receive a carry from, so a half adder — simpler, using fewer transistors than a full adder — does the complete job there without any wasted, unused carry-in logic. This is why a real multi-bit adder circuit, like the one inside a processor's arithmetic logic unit, is typically built from exactly one half adder at the bottom bit position and a chain of full adders for every bit position above it.

Read a half adder as the minimal building block of binary addition, not a complete adder in miniature: its two gates split addition's result into a same-position sum bit and a next-position carry bit, its missing carry-in is precisely what a full adder is built to add, and it remains genuinely useful on its own both as the least-significant-bit stage of a wider adder and, through its XOR half alone, as a bit-equality test wherever digital logic needs one.