gate all around transistor
**Gate-All-Around (GAA) Nanosheet Transistors** are the **successor to FinFET technology where the gate electrode wraps completely around horizontally stacked silicon channel sheets**, providing superior electrostatic control over the channel compared to the three-sided gate contact of FinFETs — enabling continued transistor scaling at 3nm and beyond where FinFETs reach their physical scaling limits.
The FinFET architecture, which dominated semiconductor manufacturing from 22nm through 5nm, relies on a tall, narrow fin where the gate wraps around three sides. As fin width narrows below ~5nm for further scaling, quantum confinement effects degrade mobility and increase variability. GAA solves this by spreading current across multiple wider sheets rather than concentrating it in an ultra-narrow fin.
**GAA Architecture**:
| Parameter | FinFET (5nm) | GAA Nanosheet (3nm) | Advantage |
|-----------|-------------|--------------------|-----------|
| **Gate contact** | 3 sides of fin | All 4 sides of sheet | Better electrostatic control |
| **Channel width** | Fixed by fin height | Tunable (sheet width) | Flexible drive strength |
| **Effective width per footprint** | Limited | Higher (stacked sheets) | Better area efficiency |
| **Subthreshold swing** | ~65-70 mV/dec | ~60-65 mV/dec | Lower leakage |
| **DIBL** | 20-30 mV/V | 10-20 mV/V | Better short-channel control |
**Nanosheet Formation Process**: The GAA process starts with alternating epitaxial layers of Si and SiGe on the substrate. After patterning (defining the transistor footprint), the SiGe layers are selectively etched away (the "channel release" step), leaving suspended Si nanosheets. The gate dielectric (high-k) and gate metal are then deposited around all surfaces of each nanosheet. Typical designs stack 3-4 sheets, each 5-7nm thick and 15-50nm wide.
**Key Process Challenges**: **Inner spacer formation** — dielectric spacers must be precisely formed in the gaps between sheets to separate the gate from the source/drain, requiring highly selective etch and deposition in confined spaces; **channel release selectivity** — SiGe removal must be perfectly selective to Si to avoid damaging the nanosheets; **uniform gate fill** — depositing gate metal uniformly in the narrow gaps (<10nm) between stacked sheets requires advanced ALD (atomic layer deposition); and **contact resistance** — wrapping contacts around multiple sheets while maintaining low resistance is more complex than single-fin contacting.
**Drive Strength Flexibility**: Unlike FinFETs (where drive strength must be quantized in units of one fin), GAA allows continuous tuning of effective channel width by varying sheet width. This enables more flexible standard cell design — a cell can use narrow sheets for low-drive and wide sheets for high-drive within the same technology, improving area efficiency compared to adding/removing discrete fins.
**GAA nanosheet transistors represent the most significant transistor architecture transition since the move from planar to FinFET — by wrapping the gate completely around the channel, they restore the electrostatic control margin that FinFETs are losing at aggressive scaling, ensuring at least two to three more generations of transistor density improvement.**