guard rings

Guard Rings Overview Guard rings are heavily doped diffusion regions surrounding sensitive circuits or I/O structures to collect injected minority carriers and prevent latch-up—a potentially destructive parasitic thyristor (PNPN) turn-on in CMOS circuits. Latch-Up Mechanism 1. CMOS structures inherently form parasitic PNPN paths (p-substrate → n-well → p-source → n-source). 2. If triggered (by ESD, power supply transients, or I/O overshoot), the parasitic thyristor latches on. 3. Low-impedance VDD-to-VSS current path forms. 4. High current can destroy the chip through thermal runaway. Guard Ring Types - N+ Guard Ring: Placed around N-well (connected to VDD). Collects minority electrons injected into the substrate before they reach the parasitic NPN base. - P+ Guard Ring: Placed around P-substrate contacts (connected to VSS). Collects minority holes before they reach the parasitic PNP base. - Double Guard Ring: Both N+ and P+ rings for maximum protection. Required around I/O cells and between NMOS/PMOS in critical areas. Where Guard Rings Are Required - I/O pad cells (highest latch-up risk from external events). - Between N-well and P-substrate regions near I/O. - Around analog circuits sensitive to substrate noise. - At boundaries between different power domains. - Foundry DRC rules specify mandatory guard ring placement. Design Rules - Guard ring width: Minimum width specified by foundry (typically 0.3-1μm). - Spacing: Guard ring must be within specified distance of the protected device. - Contact density: Frequent substrate/well contacts within the guard ring for low resistance. - Latch-up testing: JEDEC JESD78 specifies ±100mA I/O trigger current at 125°C.