latch-up

**CMOS Latch-Up** is a **parasitic thyristor (PNPN) effect inherent in bulk CMOS technology where the interaction between parasitic lateral NPN and vertical PNP bipolar transistors formed by the NMOS/PMOS well structure creates a positive feedback loop that, once triggered, shorts VDD to VSS with destructive current flow** — potentially causing permanent damage or functional failure if not designed against. The parasitic structure exists in every bulk CMOS inverter: the p-substrate, n-well, p+ source (PMOS), and n+ source (NMOS) form a PNPN thyristor. The **lateral NPN** has the NMOS n+ S/D as emitter, p-substrate as base, and n-well as collector. The **vertical PNP** has the PMOS p+ S/D as emitter, n-well as base, and p-substrate as collector. These two bipolar transistors are cross-coupled: the collector of each feeds the base of the other through the substrate and well resistance (Rsub and Rwell). If the product of their current gains (βnpn × βpnp) exceeds 1 and sufficient current flows through Rsub or Rwell to forward-bias either parasitic emitter-base junction, regenerative feedback locks the structure into a high-current latched state. Latch-up can be triggered by: **voltage overshoot/undershoot** on I/O pins (exceeding VDD or going below VSS forward-biases parasitic junctions); **power supply sequencing** errors (one supply powered before another creates injection conditions); **radiation strikes** (single-event latch-up, SEL — ionizing radiation generates minority carriers that trigger the thyristor); and **internal noise** (large current transients coupling through substrate resistance). Prevention and design-against measures include: **Guard rings** — n+ guard rings in n-well (connected to VDD) collect injected minority carriers before they reach the PNP base, and p+ guard rings in p-substrate (connected to VSS) collect electrons before reaching the NPN base. Guard rings reduce Rwell and Rsub, increasing the holding current needed to sustain latch-up. **Well and substrate contacts** — frequent tap cells (VDD/VSS contacts to well/substrate) placed every 10-30μm reduce local resistance and suppress parasitic bipolar gain. **Retrograde well profiles** — buried high-concentration well implant reduces the sheet resistance of the well, lowering the voltage drop that forward-biases parasitic junctions. **Deep n-well isolation** — placing a buried n-well beneath the p-well creates a fully isolated p-well, breaking the PNPN current path. **SOI technology** — fully or partially depleted SOI eliminates latch-up entirely by physically isolating NMOS and PMOS in separate silicon islands surrounded by buried oxide. Latch-up testing follows **JEDEC/JESD78** standards: both positive and negative current injection (typically ±100mA) and voltage overshoot tests (VDD+1.5V) at elevated temperature (125°C, worst case due to higher bipolar gain). I/O cells require dedicated latch-up guard ring structures verified both in layout and by foundry DRC rules. **CMOS latch-up prevention is a fundamental reliability discipline — the same parasitic bipolar transistors that exist in every bulk CMOS circuit must be systematically neutralized through layout, process, and circuit design techniques to prevent this potentially destructive failure mode.**