esd latchup prevention

**CMOS Latch-Up Prevention** is the **circuit and layout engineering discipline that prevents the parasitic PNPN thyristor structure inherent in every CMOS circuit from triggering into a destructive low-impedance state — where a single latch-up event can draw unlimited current from the power supply, permanently damaging metal interconnects and junction regions within microseconds if not interrupted by current-limiting or power cycling**. **The Parasitic Thyristor** In every CMOS inverter, the PMOS (in N-well) and NMOS (in P-substrate) form a parasitic lateral PNPN structure: P+ source (PMOS) → N-well → P-substrate → N+ source (NMOS). This is equivalent to a cross-coupled PNP/NPN transistor pair (thyristor/SCR). Under normal operation, both parasitic BJTs are off. If either BJT is triggered (by substrate or well current injection), positive feedback between the two BJTs latches the structure into a low-impedance state — effectively shorting VDD to VSS through the silicon. **Latch-Up Triggers** - **I/O Over/Under-Voltage**: An input signal that exceeds VDD or goes below VSS forward-biases a well-substrate junction, injecting current into the well or substrate. - **ESD Events**: ESD pulses inject large currents through substrate/well that trigger the parasitic BJTs. - **Power Supply Sequencing**: If I/O pins are driven before VDD is stable, the input protection diodes forward-bias, injecting well/substrate current. - **Radiation (SEL — Single Event Latch-up)**: High-energy particles (cosmic rays, alpha particles) generate electron-hole pairs along their track, creating the trigger current. Critical for aerospace applications. **Prevention Strategies** - **Guard Rings**: The primary prevention mechanism. P+ guard rings tied to VSS surround NMOS devices, collecting injected holes before they reach the N-well. N+ guard rings tied to VDD surround PMOS devices, collecting injected electrons before they reach the P-substrate. Foundry DRC rules specify minimum guard ring width, spacing, and contact density. - **Well and Substrate Taps**: Frequent N-well-to-VDD and P-substrate-to-VSS contacts reduce the local well/substrate resistance (Rwell, Rsub), lowering the voltage drop that triggers BJT turn-on. Tap spacing rules (typically every 10-20 um) are mandatory in DRC. - **Retrograde Wells**: Deep, heavily-doped well implants reduce the vertical base resistance of the parasitic BJT, increasing the trigger current threshold. Standard at all nodes ≤65nm. - **SOI (Silicon-on-Insulator)**: The buried oxide layer completely eliminates the vertical PNPN path, making SOI inherently latch-up immune. A key advantage of SOI processes for radiation-hard and automotive applications. **Testing** JEDEC JESD78 defines the standard latch-up test: positive and negative current injection (±100 mA) at every I/O pin, and power supply overvoltage (VDD + 0.5V to 1.5V). The device must not latch under any of these conditions up to 125°C. CMOS Latch-Up Prevention is **the foundational reliability discipline that tames the parasitic thyristor lurking inside every CMOS circuit** — because without proper guard rings, well contacts, and design rules, any CMOS chip is one over-voltage event away from self-destruction.