esd latchup prevention

**CMOS Latch-Up Prevention** is the **circuit design and process engineering discipline that prevents the triggering of parasitic PNPN thyristor structures inherent in the CMOS well architecture — where a triggered latch-up event creates a low-impedance path between VDD and VSS that can draw catastrophic current (hundreds of milliamps to amps), destroying the chip within milliseconds unless the power supply current is externally limited or interrupted**. **The Parasitic Thyristor** In a standard CMOS inverter, the PMOS (in N-well) and the NMOS (in P-substrate) are separated by the well junction. The substrate and well doping profiles create two parasitic bipolar transistors — a lateral PNP (emitter=P+ S/D in N-well, base=N-well, collector=P-substrate) and a vertical NPN (emitter=N+ S/D in P-substrate, base=P-substrate, collector=N-well). These two transistors are cross-coupled, forming a PNPN thyristor (SCR). If both transistors reach sufficient gain (product of current gains beta_PNP × beta_NPN ≥ 1), positive feedback locks the structure into a low-impedance conducting state. **Triggering Mechanisms** - **ESD Events**: High-voltage transients on I/O pins inject minority carriers into the substrate or well, forward-biasing the parasitic BJT base-emitter junctions. - **Power Supply Transients**: Supply voltage overshoot or undershoot during power-up can momentarily forward-bias the well-substrate junction. - **Radiation (Single Event Latch-up, SEL)**: An energetic particle (cosmic ray, heavy ion) passing through the silicon generates a dense column of electron-hole pairs that triggers the thyristor. Critical for space and avionics applications. - **Internal Noise**: High dI/dt from simultaneously-switching outputs creates substrate/well bounce that can trigger latch-up in nearby circuits. **Prevention Strategies** - **Guard Rings**: N+ guard rings in the N-well (connected to VDD) collect injected minority carriers before they reach the parasitic PNP base. P+ guard rings in the substrate (connected to VSS) collect carriers before they reach the NPN base. Guard rings are mandatory around I/O cells and between NMOS/PMOS in sensitive areas. - **Well and Substrate Contacts**: Frequent, closely-spaced well taps (N+ to VDD in N-well) and substrate taps (P+ to VSS in P-substrate) reduce the local well/substrate resistance, preventing voltage buildup that would forward-bias the parasitic junctions. Design rules specify maximum tap-to-tap spacing (~10-25 um). - **Retrograde Well Profiles**: Heavily-doped deep wells with lightly-doped surface reduce the lateral parasitic BJT gain by increasing the base doping relative to the emitter. This directly reduces beta and makes latch-up harder to trigger. - **Deep N-well (Triple-Well)**: An additional deep N-well isolates the P-substrate from the surface P-well, breaking the parasitic thyristor chain. Required for noise-sensitive analog circuits and I/O cells. - **EPI Substrates**: Lightly-doped epitaxial silicon on a heavily-doped substrate provides a low-resistance ground plane that shunts parasitic current and prevents latch-up triggering. **Testing** JEDEC JESD78 defines latch-up qualification: every I/O pin must withstand ±100 mA injection current (trigger test) and ±1.5× VDD overvoltage (supply overvoltage test) without entering latch-up. Automotive (AEC-Q100) requires testing at 125°C junction temperature (worst case for BJT gain). CMOS Latch-Up Prevention is **the design discipline that keeps the parasitic thyristor sleeping** — ensuring that the cross-coupled bipolar transistors lurking in every CMOS well structure never receive enough stimulus to lock into the catastrophic feedback loop that would destroy the chip.