latch-up

Latch-up is a parasitic thyristor (PNPN) activation in CMOS circuits where a trigger event causes a low-impedance path between VDD and VSS, drawing excessive current that can destroy the device. Mechanism: inherent parasitic bipolar transistors in CMOS—vertical PNP (PMOS N-well to substrate) and lateral NPN (NMOS N-well to substrate) form a thyristor structure. Trigger: (1) Input/output voltage exceeding VDD or below VSS (pin overshoot/undershoot); (2) Supply transients—fast VDD ramp; (3) Ionizing radiation (SEL—single event latch-up in space applications); (4) ESD events; (5) Junction forward bias from minority carrier injection. Latch-up sequence: (1) Trigger injects minority carriers; (2) Parasitic NPN or PNP turns on; (3) Positive feedback—each transistor drives the other's base; (4) Regenerative loop—both transistors saturate; (5) High current path VDD→PMOS well→substrate→VSS. Consequences: (1) Destructive—metal melting, junction damage from high current; (2) Non-destructive—functional failure, requires power cycle. Prevention (process): (1) Guard rings—N+ and P+ rings around NMOS/PMOS to collect minority carriers; (2) Deep N-well—isolate P-substrate from parasitic NPN; (3) Heavy well doping—reduce substrate/well resistance (reduce bipolar gain); (4) Retrograde wells—high doping at depth; (5) SOI—complete isolation eliminates parasitic thyristor. Prevention (design): (1) I/O clamp diodes—prevent voltage excursions; (2) ESD protection—limit current injection; (3) Power sequencing—avoid input before VDD. Testing: JEDEC JESD78—apply trigger current to I/O pins at elevated temperature, verify no sustained high current. Latch-up immunity is a critical qualification requirement, especially for automotive and industrial applications.