hardware emulation
**Hardware Emulation** is the **use of specialized hardware platforms (FPGA arrays or custom processors) to execute RTL designs at speeds 100-10,000x faster than software simulation** — enabling full-chip SoC verification, firmware co-verification, and real-world stimulus testing that would take years to run in conventional simulation.
**Why Emulation?**
- **Software simulation**: ~1-100 Hz for a full SoC — a single boot sequence takes hours/days.
- **Hardware emulation**: ~100 KHz to 10 MHz — boot Linux in minutes, run real software.
- **FPGA prototyping**: ~10-200 MHz — nearest to real speed but less debug visibility.
**Speed Comparison**
| Method | Speed (SoC-level) | Debug Visibility | Capacity |
|--------|-------------------|-----------------|----------|
| RTL Simulation | 1-100 Hz | Full signal access | Any size |
| Emulation | 100 KHz – 10 MHz | Selective probes | < 20B gates |
| FPGA Prototyping | 10-200 MHz | Limited | < 2B gates |
| Silicon | GHz | Very limited | N/A |
**Major Emulation Platforms**
- **Cadence Palladium Z2/Z3**: Industry leader. Custom processor-based architecture. Up to 15B+ gate capacity.
- **Siemens Veloce Strato/primo**: Processor-based. Strong in automotive/safety verification.
- **Synopsys ZeBu EP1**: FPGA-based emulator. Highest raw speed but less debug flexibility.
**Emulation Use Cases**
- **Firmware Co-Verification**: Run actual embedded software (firmware, drivers, RTOS) on the RTL design before silicon.
- Critical for catching HW/SW integration bugs that simulation can't reach.
- **Full-Chip Power Analysis**: Generate realistic switching activity for power estimation.
- **Protocol Compliance**: Run USB, PCIe, Ethernet compliance test suites against the design.
- **Long-Running Scenarios**: Stress tests, security fuzzing, boot sequences.
**Emulation Cost**
- Entry-level emulator: $5-10M.
- Full data center deployment: $50-200M+ (shared across many design teams).
- Cost justified by: catching bugs before tapeout saves $10-50M per respin.
**Compile Time**
- Emulation compilation (synthesis to emulator): 12-72 hours for a large SoC.
- Any RTL change requires recompilation — incremental compile techniques reduce this.
Hardware emulation is **essential infrastructure for modern SoC verification** — the complexity of billion-gate designs with embedded processors, full software stacks, and real-world interfaces makes it impossible to reach sufficient verification coverage with simulation alone.