Hmos 1978 Push Second Generation Hmos Ii Confront Own Limit

# Step 8 — Push HMOS Into a Second Generation (HMOS-II) and Confront Its Own Limit

## 1. The 2-Micron Push: Velocity Saturation and Hot-Carrier Avalanche

When Intel pushed fixed-voltage scaling into its second generation (HMOS-II in 1979), the $E = V/L$ field constraint reasserted itself with unyielding physical force. In Step 1, we defined why shrinking channel length while holding supply voltage at $V_{dd} = 5.0\ \text{V}$ breaks ideal constant-field scaling. In Steps 2 through 7, we saw how process innovations—ion implantation, $70\ \text{nm}$ oxides, polycide wiring, and double polysilicon—temporarily accommodated this strain, yielding the 8 MHz Intel 8086.

Eager to maintain its performance lead, Intel scaled the architecture further in 1979, introducing HMOS-II:
* Channel Length ($L$): Scaled from $3.5\ \mu\text{m}$ down to $2.0\ \mu\text{m}$ (with electrical effective length $L_{\text{eff}} \approx 1.5\ \mu\text{m}$).
* Gate Oxide Thickness ($t_{\text{ox}}$): Thinned from $70\ \text{nm}$ down to $40\ \text{nm}$ ($400\ \text{Å}$).
* Junction Depth ($x_j$): Reduced to $0.4\ \mu\text{m}$.
* Supply Voltage ($V_{dd}$): Still rigidly held at $5.0\ \text{V}$ due to the commercial requirement for TTL system bus compatibility.

At $L = 2.0\ \mu\text{m}$, the internal lateral electric field exceeded the critical threshold where silicon physics breaks down:

$$E_{\parallel} = \frac{V_{dd}}{L} = \frac{5.0\ \text{V}}{2.0\ \mu\text{m}} = 25\ \text{kV/cm} \gg E_{\text{crit}} \approx 10\ \text{kV/cm}$$

Near the drain pinch-off region, localized peak fields climbed past $150\ \text{kV/cm}$. This extreme field triggered two severe physical degradation mechanisms:
1. Velocity Saturation ($v_{\text{sat}}$): Electrons accelerating in the channel suffered intense optical phonon scattering, capping drift velocity at $v_{\text{sat}} \approx 10^7\ \text{cm/s}$. Instead of saturation current scaling inversely with channel length ($I_{\text{sat}} \propto 1/L$), current scaled linearly with gate overdrive:

$$I_{\text{sat}} \approx W C_{\text{ox}} v_{\text{sat}} (V_{GS} - V_T)$$

The transconductance speedup from shrinking $L$ diminished rapidly.
2. Impact Ionization and Substrate Current: Channel electrons acquiring kinetic energies exceeding the silicon bandgap ($1.1\ \text{eV}$) caused impact ionization, creating secondary electron-hole pairs. High-energy electrons ($> 3.2\ \text{eV}$) surmounted the $\text{Si-SiO}_2$ potential barrier and injected into the gate dielectric, causing threshold voltage drift ($\Delta V_T$), while generated holes created massive substrate current ($I_{\text{sub}}$) that threatened chip ground stability.

HMOS-II at 2.0 µm: The Re-Emergence of the Field Wall velocity saturation, hot-carrier avalanche, and substrate current under 5V fixed-voltage stress DEVICE COLLISION: L = 2.0 µm AT 5.0 V Source 0 V Drain 5.0 V Channel (L = 2.0 µm) tox = 40 nm (E⊥ = 1.25 MV/cm) Polycide Gate (5.0 V) Epeak > 150 kV/cm HCI Trap (ΔVT) Isub (Substrate Current) Physical Breakdown Under 5V: • Velocity saturation limits current • Impact ionization generates substrate noise THE TRIO OF PHYSICAL CEILINGS 1. Velocity Saturation Ceiling: • Carrier drift velocity hits hard limit: vsat ≈ 1×10⁷ cm/s • Drive current scales linearly with VGS − VT, not quadratically 2. Hot-Carrier Reliability Ceiling: • Trapping at oxide interface shifts threshold: ΔVT > 100 mV • Long-term degradation limits operating lifespan to < 3 years 3. Substrate Current Ceiling: • Peak substrate current climbs into milliampere range per die • Causes ground-bounce noise and triggers unintended parasitic turns Requires expensive on-chip substrate bias generators (VBB pump). THE FINAL NMOS DEVICE CRUNCH ✓ Diminishing Transconductance Returns: Velocity saturation eliminated the speed advantage of further channel shrinking ✓ Reliability Crisis: Hot carriers and substrate current proved that 5V operation below 2 µm was physically unsustainable HMOS-II was the ultimate expression of fixed-voltage NMOS—and the proof that it could scale no further.

## 2. The Thermodynamic Wall: Static Power Dissipation

Beyond device physics, ratioed NMOS logic collided with a thermodynamic wall. Because a depletion-load inverter draws continuous DC power whenever its output is logic-low, total static power scales linearly with active transistor count:

$$P_{\text{chip}} \approx N_{\text{gates}} \cdot \alpha \cdot \left(\frac{1}{2} I_{\text{load}} V_{dd}\right) + C_{\text{tot}} V_{dd}^2 f$$

In the 1978 Intel 8086 (29,000 transistors at 8 MHz), total chip dissipation reached $1.5\text{--}1.8\ \text{W}$. Standard ceramic and plastic Dual In-line Packages (DIP) could dissipate at most $2.0\text{ to }2.5\ \text{W}$ in ambient air without active cooling.

Extrapolating this curve to next-generation microprocessors (the 134,000-transistor Intel 80286 and 275,000-transistor 80386) revealed an unmanageable power catastrophe: an NMOS 80386 would dissipate over $10\text{--}15\ \text{W}$—melting plastic packages and boiling circuit junctions.

The Thermodynamic Wall: Microprocessor Static Power Scaling ratioed NMOS static dissipation exploding past the 2.5W DIP package thermal dissipation limit CHIP POWER DISSIPATION VS. TRANSISTOR COUNT Transistors Power (W) DIP Package Thermal Limit (2.5 W) THERMAL MELTDOWN ZONE Ratioed NMOS CMOS (Zero DC Power) 8080 (0.8W) 8086 (1.8W) NMOS 80286 (~5W!) The Power Accounting Reality: • A 29,000-transistor HMOS processor pressed against the 2.5W packaging limit • Microprocessors could not scale past 100,000 transistors without abandoning ratioed NMOS THE INEVITABLE PIVOT Why NMOS Was Doomed: • 50% of inverters ON at any time • Pull-up current drains continuously • Static dissipation: PDC ∝ Ngates No circuit trick could eliminate this. Why CMOS Was the Savior: • Complementary switches: PDC ≈ 0 • Current flows only during switching ✓ Power scales with clock, not gate count Set up the 1984 CMOS revolution. The Architectural Epilogue of HMOS-II: HMOS-II pushed NMOS to its physical limit (2.0 μm, 10 MHz), proving that constant-voltage scaling had reached its end and ensuring that the future of VLSI belonged to CMOS.

## 3. Place This Step in the Project's Own Lineage

Step 8 documents the boundary condition where an architectural paradigm exhausts its physical runway:
1. The Culmination and Collapse of Fixed-Voltage Scaling: Steps 1 through 7 traced the meteoric rise of HMOS as the semiconductor industry’s champion technology. Step 8 demonstrates what happens when the underlying premise—holding $V_{dd} = 5.0\ \text{V}$ while shrinking channel length—is pushed too far. At $L = 2.0\ \mu\text{m}$ (HMOS-II), velocity saturation eliminated drive-current speedups, hot carriers degraded oxide reliability, and substrate currents introduced internal circuit noise.
2. The Thermal Meltdown Barrier: Even if device physics could have tolerated $1.5\ \mu\text{m}$ channel lengths, packaging thermodynamics could not. Ratioed NMOS logic burned continuous DC power. At 29,000 transistors, the Intel 8086 was already consuming $1.8\ \text{W}$ in a 2.5 W package; scaling to the 134,000 transistors of the 80286 would have generated over 5 W, melting standard packaging.
3. Setting Up the Industrial Crossover: In Step 9, we examine the direct historical confrontation between this dying NMOS path and the parallel CMOS branch it had competed with since 1963, explaining why NMOS dominated the 1970s on density and cost, and precisely what triggered the historic industry-wide crossover to CMOS in the early 1980s.

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