implant anneal activation
**Implant Anneal and Dopant Activation** is the **high-temperature thermal process that repairs crystal damage from ion implantation and electrically activates dopant atoms by moving them from interstitial positions onto substitutional lattice sites** — where the anneal temperature, duration, and ramp rate determine the tradeoff between maximizing dopant activation (higher temperature) and minimizing dopant diffusion (shorter time) that defines the junction depth and abruptness of modern transistors.
**Why Anneal Is Needed After Implant**
- Ion implantation damages the silicon crystal lattice — creates amorphous regions.
- Implanted atoms sit in interstitial (non-electrically-active) positions.
- Without anneal: Sheet resistance is very high, no useful junction forms.
- Anneal: Recrystallizes silicon, moves dopants to substitutional sites → electrically active.
**Anneal Types for Advanced CMOS**
| Anneal Type | Temperature | Time | Activation | Diffusion |
|------------|-----------|------|-----------|----------|
| Furnace Anneal | 800-1000°C | 30-60 min | Good | Very High |
| Rapid Thermal Anneal (RTA) | 900-1100°C | 1-30 sec | Good | Moderate |
| Spike Anneal | 1000-1100°C | ~1 ms at peak | Very Good | Low |
| Millisecond Anneal (MSA) | 1100-1400°C | 0.1-1 ms | Excellent | Very Low |
| Laser Anneal | 1200-1400°C | μs-ns pulse | Excellent | Minimal |
**Spike Anneal (Current Standard)**
- Rapid ramp to peak temperature (150-250°C/sec) → hold for < 1 second → rapid cool.
- Peak temperature: 1000-1100°C depending on dopant species.
- Provides high activation with controlled diffusion — standard for S/D junctions at 28nm and below.
**Millisecond and Laser Anneal**
- Heat only the wafer surface for < 1 ms — bulk wafer remains cold.
- Ultra-high temperature (1200-1400°C) achieves near-solid-solubility activation.
- Diffusion: < 1 nm lateral spread — enables ultra-shallow junctions (< 10 nm).
- Used as supplementary anneal after spike — boosts activation without additional diffusion.
**Dopant Activation Levels**
| Dopant | Solid Solubility (~1050°C) | Typical Activation |
|--------|--------------------------|-------------------|
| Boron (B) | ~2 × 10²⁰ cm⁻³ | 60-80% of dose |
| Phosphorus (P) | ~5 × 10²⁰ cm⁻³ | 70-90% of dose |
| Arsenic (As) | ~2 × 10²¹ cm⁻³ | 80-95% of dose |
**Transient Enhanced Diffusion (TED)**
- Implant damage releases silicon interstitials.
- Interstitials enhance boron diffusion by 10-100x during initial anneal → junction spreads uncontrollably.
- Mitigation: Co-implant carbon or nitrogen to trap interstitials. Use MSA to outrun TED kinetics.
Implant anneal is **one of the most critical thermal steps in the CMOS process** — the ability to achieve high dopant activation while maintaining ultra-shallow, abrupt junctions defines the transistor's drive current, leakage, and threshold voltage control at every advanced process node.