Intel-18a

Intel 18A is the platform where Intel changed its transistor architecture entirely, moving from the FinFET gate used across Intel 7, Intel 4, and Intel 3 to a gate-all-around device Intel calls RibbonFET, and pairing it with backside power delivery Intel calls PowerVia — two separate engineering decisions bundled into one node name, the same pattern TSMC's A16 follows with its own nanosheet-plus-backside-power combination. At a high level, how 18A reached that combination looks like this:

A few things are worth knowing about why 18A is two stacked decisions, not one physical measurement:

RibbonFET and PowerVia address two different constraints, and both had to work together before 18A could qualify. RibbonFET wraps the gate around a thin semiconductor channel on all sides, restoring electrostatic control that a FinFET loses as channels shrink, while PowerVia moves power-rail wiring to the wafer's backside so it stops competing with signal wiring on the front-side metal stack — a design choice unrelated to the gate shape itself, since a nanosheet transistor can run with front-side power just as N2 does for TSMC. Intel reported targeting 2025 for 18A volume production, with Panther Lake positioned as an early client product and Intel Foundry pursuing external customers for the same platform.

18A marks Intel's biggest architecture break since the FinFET era began, which is why it followed Intel 3 by a wider gap than Intel 3 followed Intel 4. Every node from Intel 7 through Intel 3 kept the same FinFET gate, refining lithography, interconnect, and process tuning around it — 18A is the point where Intel had to requalify an entire design ecosystem from scratch: new standard-cell libraries, new extraction models, new physical-verification rules suited to a wrapped gate and a backside power path simultaneously. That larger engineering step is also why 18A's qualification timeline runs noticeably longer than the gap between Intel 4 and Intel 3.

Intel Foundry's push to win external customers makes 18A's qualification evidence matter more than any prior Intel node's did. Unlike Intel 7 through Intel 3, which mostly shipped Intel's own products, 18A is central to Intel's strategy of selling foundry services to outside customers who need the same PDK maturity, yield data, and packaging support that TSMC and Samsung already provide their fabless customers — a roadmap date for 18A should be read as a target revisable against technical and business conditions, the same caution every other node in this series requires.

Comparing 18A against TSMC's N2 or A16 by name alone repeats the exact mistake this whole series keeps warning against. 18A's RibbonFET and TSMC's N2 nanosheet gate both solve the same electrostatic problem with a similar gate-all-around approach, and 18A's PowerVia and TSMC's A16-era backside power pursue the same wiring-congestion relief — but neither pairing proves the two platforms share a gate pitch, a yield curve, or a timeline. A credible cross-company comparison needs the same circuit-level, matched-workload evidence this entire series insists on.

Read Intel 18A through a *stacked-decision* lens rather than a *nanometer* lens: 18A is RibbonFET's gate-all-around transistor plus PowerVia's backside-power integration, reported on Intel's own 2025 qualification timeline — not a single physical measurement the name implies. 18A's two-part design is the same underlying fact as Intel 3's refinement of Intel 4 and TSMC's A16 pairing N2's transistor with its own backside power: a process node name is a company's own platform, not a ruler the rest of the industry shares.