isolation cell

**An isolation cell** is a special standard cell that **clamps its output to a known safe value** (logic 0 or logic 1) when its associated power domain is shut down — preventing the unpowered domain's floating, undefined outputs from corrupting the logic of neighboring powered-on domains. **Why Isolation Is Necessary** - When a power domain is gated off (power switches disconnected), the flip-flops and gates in that domain lose their supply voltage. - The outputs of the powered-off domain become **undefined** — they may float to any voltage, oscillate, or settle at intermediate levels. - These garbage values propagate to the powered-on logic connected to them, causing: - **Functional Errors**: Downstream logic receives random inputs → incorrect computation. - **Short-Circuit Current**: Intermediate voltage levels at receiver inputs cause both PMOS and NMOS to conduct → excessive current draw. - **Latch-Up Risk**: Unexpected voltage levels can trigger parasitic SCR paths. - Isolation cells **clamp** the output to a defined value before the domain powers down, and hold it there throughout the power-off period. **Isolation Cell Operation** - **Normal Mode (ISO = 0)**: The isolation cell is transparent — it passes the input signal to the output like a buffer. - **Isolation Mode (ISO = 1)**: The output is forced to a fixed value (0 or 1) regardless of the input. - **Sequencing**: The isolation signal must be asserted **before** the power switches turn off, and de-asserted **after** the power domain is fully powered up. **Isolation Cell Types** - **Clamp-Low Isolation**: Output forced to logic 0 during isolation. Uses AND-based logic: output = data AND (NOT ISO). - **Clamp-High Isolation**: Output forced to logic 1. Uses OR-based logic: output = data OR ISO. - **Latch Isolation**: The output latches the last valid value before power-down — preserves the most recent state instead of forcing 0 or 1. **Isolation Cell Power Supply** - The isolation cell must remain **powered on** while the source domain is off — it is connected to the **always-on supply** (or the receiving domain's supply). - The input side connects to the powered-off domain. - The output side connects to the powered-on domain. **Isolation in the Design Flow** - **UPF/CPF**: The power intent file specifies which domain boundaries need isolation, the isolation type (clamp-0 or clamp-1), and the isolation control signal. - **Automatic Insertion**: Synthesis/P&R tools insert isolation cells at every output port of a power-gated domain. - **Placement**: Typically placed at the boundary between power domains — on the "always-on" side. - **Verification**: Power-aware verification tools check that: - Every output of a power-gated domain has an isolation cell. - The isolation control signal is asserted in the correct sequence relative to power switching. - The clamped value is functionally correct for the receiving logic. Isolation cells are **essential safety infrastructure** for power-gated designs — they prevent the chaos of floating signals from propagating across domain boundaries and corrupting the chip's functional behavior.