layout versus schematic (lvs) clean

**LVS clean** means the **Layout Versus Schematic** verification has passed with **zero errors** — confirming that the physical layout (mask data) correctly implements the intended circuit schematic with all connections, devices, and parameters matching exactly. **What LVS Checks** - **Netlist Extraction**: The LVS tool extracts a circuit netlist from the physical layout by recognizing device shapes (transistors, resistors, capacitors) and tracing metal connectivity. - **Comparison**: The extracted netlist is compared against the original schematic netlist (from the circuit designer), checking: - **Device Match**: Every transistor, resistor, capacitor in the schematic exists in the layout with correct type and parameters (W/L, resistance, capacitance). - **Net Match**: Every electrical connection in the schematic corresponds to a physical connection in the layout. - **No Extra Devices**: The layout doesn't contain unintended devices (parasitic transistors from overlapping layers). - **No Extra Nets**: No unintended connections (short circuits) or missing connections (open circuits). **Common LVS Errors** - **Opens**: A net that should be connected is physically disconnected — missing via, broken routing, unconnected pin. - **Shorts**: Two nets that should be separate are physically connected — overlapping metal, unintended contact. - **Device Mismatches**: Wrong transistor width/length, missing devices, extra devices. - **Property Mismatches**: Device parameters (multiplier, finger count) don't match between schematic and layout. - **Floating Nets**: Nodes not connected to any device terminal. **LVS in the Design Flow** - LVS is performed **after layout is complete** but before tapeout. - **Mandatory**: No design is taped out without LVS clean status. It is a non-negotiable sign-off requirement. - Often iterated multiple times as layout errors are found and corrected. - **DRC + LVS**: Both Design Rule Check and LVS must pass — DRC ensures manufacturability, LVS ensures correctness. **LVS Tools** - **Calibre** (Siemens/Mentor): Industry standard, most widely used. - **Assura/PVS** (Cadence): Integrated with Virtuoso layout environment. - **ICV** (Synopsys): Integrated with IC Compiler. **LVS for Different Design Styles** - **Custom/Analog**: Full transistor-level LVS — every device individually verified. - **Digital (Standard Cell)**: Cell-level LVS is done during library development. Top-level LVS verifies cell placement and routing. - **Mixed-Signal**: Both custom analog blocks and digital P&R blocks verified together. LVS clean is the **fundamental correctness guarantee** in IC design — it proves that what was designed is what will be manufactured.