layout versus schematic

**Layout vs. Schematic (LVS)** is the **automated verification that layout and schematic netlist represent identical circuit — extracting devices and nets from layout, comparing topology and connectivity to schematic — catching design errors (shorts, opens, mismatches) before fabrication**. LVS is mandatory sign-off. **Device and Net Extraction from Layout** Layout consists of geometric shapes (polygons) on multiple layers (metal, gate, diffusion, contact). LVS extracts devices (transistors, resistors, capacitors) and nets by: (1) recognizing layer patterns — gate polygon + diffusion polygon + contact = transistor, (2) recognizing interconnect — metal polygon = net segment, contact = layer via, (3) building connectivity — tracing metal/via connections to establish net topology. Extracted schematic is generated from layout geometry. **Comparison with Design Schematic** Extracted schematic (from layout) is compared to design schematic (provided by designer) for: (1) device count — same number of transistors, resistors, etc., (2) device connections — each device terminal connected to correct nets, (3) net topology — matching net connectivity. If discrepancies exist, LVS declares a mismatch (fail). **Shorts and Opens** LVS errors commonly include: (1) shorts — two nets unintentionally connected (layout shorting bar or missing spacing between metal), (2) opens — net broken mid-path (metal bridge open-circuited, via missing, contact missing), (3) floating nodes — net not connected to any power/ground, causing undefined behavior. Shorts cause functional failure (incorrect logic values); opens cause failures (stuck-at logic), floating nodes cause oscillation/metastability. **Node Correspondence** LVS identifies each net/node in layout and matches to corresponding node in schematic. Nodes are typically named (e.g., 'vdd', 'gnd', 'data_bus[7:0]'). If schematic node 'A' is split into two separate metal regions in layout (accidentally), LVS detects two layout nodes matching one schematic node, declaring a short (or node split error, depending on tool). **Device Recognition** LVS recognizes device types from layout geometry patterns: (1) transistor — gate polygon overlapping diffusion polygon (forming channel), (2) resistor — poly or metal resistor bar (specific layer combination), (3) capacitor — two conductive layers separated by dielectric (e.g., metal-insulator-metal, MIM capacitor), (4) diode — junction region (p-type + n-type diffusion). Device recognition requires technology-specific rule set (LVS rule file) that defines layer combinations for each device type. **Calibre LVS (Siemens)** Calibre LVS is industry-standard from Siemens (formerly Mentor, merged with Siemens). Calibre provides: (1) fast LVS (minutes to hours for full chip), (2) flexible rule engine (user-defined device recognition), (3) debugging tools (visual, hierarchical comparison), (4) integration with design flows (Innovus, ICC2, others). Calibre LVS is adopted by >80% of foundries and design teams. Alternative: IC Validator (Synopsys), but Calibre dominates. **Hierarchical LVS vs Flat** Hierarchical LVS compares block-by-block (respects design hierarchy), improving verification speed and enabling block-level debugging. Flat LVS flattens hierarchy and verifies entire chip at once (slower but can catch cross-hierarchy issues). Most designs use hierarchical LVS (fast, manageable), with selective flat LVS for critical blocks (interfaces). **LVS Debug Flow** LVS failures require debugging: (1) identify failing net/device, (2) inspect layout geometry (view in layout editor), (3) identify root cause (shorts, opens, misconnections), (4) fix design/layout, (5) re-run LVS. LVS debugging tools (Calibre) provide visual debugging: highlight failing nets in layout, show expected vs actual connections. Complex failures require manual inspection and careful analysis of layer stack and geometry. **Post-LVS Parasitics** After LVS passes, extracted parasitics (R, C) are optionally extracted for sign-off. Post-LVS parasitics are based on verified netlist (matched to layout), so parasitic extraction is performed on confirmed-correct circuit. Post-LVS parasitics enable accurate timing simulation and power analysis. **Mismatches and Error Categories** Common LVS error categories: (1) device count mismatch — different number of transistors in layout vs schematic, (2) node count mismatch — different number of nets, (3) device property mismatch — transistor width/length differs from schematic, (4) power/ground connectivity — missing or extra supply connections, (5) pin assignment — layout net doesn't match schematic pin name. Designer must resolve mismatches by (1) fixing layout (if layout is wrong) or (2) updating schematic (if design intent changed). **LVS for Hard Macros and RAMs** Hard macros (memory blocks, analog cores) often have LVS bypassed: (1) memory compiler-generated SRAM has guaranteed correctness (compiler-produced, matches specification), (2) analog blocks (op-amp, comparator) may be hand-drawn, requiring selective LVS (only top-level port connectivity verified). LVS rules are customized for special cells: (1) SRAM LVS skips internal cell details (trust compiler), (2) analog LVS matches schematic at top level only. **Summary** LVS is an essential verification step, catching design errors before expensive fabrication. Continued development in tool speed and debugging capabilities enables efficient closure of complex hierarchical designs.