lvs check

**LVS (Layout vs. Schematic)** — verifying that the physical layout correctly implements the intended circuit by comparing extracted layout connectivity against the original schematic/netlist. **What LVS Checks** - Every transistor in the netlist exists in the layout (and vice versa) - All connections match (no missing wires, no shorts) - Device parameters match (width, length, number of fins) - No extra or missing devices **Process** 1. **Extract**: Tool reads layout geometry and identifies devices and connectivity 2. **Compare**: Extracted netlist vs. source netlist (from synthesis) 3. **Report**: List all mismatches — opens, shorts, missing devices, parameter mismatches **Common Errors** - **Short**: Two nets that shouldn't be connected are touching - **Open**: A net that should be continuous is broken - **Missing device**: Transistor in netlist not found in layout - **Parameter mismatch**: Wrong transistor width or number of fins **Tools**: Siemens Calibre (gold standard), Synopsys IC Validator, Cadence Pegasus **LVS Clean = Layout Matches Design** - Must be 100% clean before tapeout - Automated PnR tools generally produce LVS-clean layouts - Manual edits (ECOs) are the main source of LVS errors **LVS** is the ultimate sanity check — it guarantees the manufactured chip will contain the circuit the designers intended.