ler/lwr impact

Line edge roughness (LER) and line width roughness (LWR) are stochastic variations in the edges and width of patterned features, causing transistor variability that worsens with each technology node. Definitions: (1) LER—3σ variation of one edge from ideal straight line; (2) LWR—3σ variation of line width (= √2 × LER if edges uncorrelated). Physical origin: (1) Photon shot noise—statistical variation in photon count during exposure (fewer photons per pixel as features shrink); (2) Resist chemistry—molecular-level randomness in acid generation, diffusion, and dissolution; (3) Etch transfer—plasma etch can smooth or amplify resist roughness. Typical values: LER ≈ 1.5-3.0nm 3σ for EUV, 2-4nm for ArF immersion. Impact on transistors: (1) Gate CD variation—LWR on gate directly modulates Lgate, affecting Vt and drive current; (2) Fin width variation—LWR on fin patterning changes FinFET channel width; (3) Nanosheet width variation—affects GAA drive current; (4) Contact/via edge roughness—varies contact resistance. As fraction of feature: at 5nm node with ~20nm gate length, 3nm LER is 15% variation—significant impact on electrical uniformity. LER vs. node: LER has not scaled proportionally with feature size (physical floor from resist chemistry)—relative impact grows each node. Mitigation: (1) EUV—higher photon energy but fewer photons (shot noise trade-off); (2) High-sensitivity resists—more photon-efficient; (3) Post-lithography smoothing—plasma or chemical treatments; (4) Self-aligned patterning—spacer-defined edges smoother than resist-defined; (5) Design—larger features where possible, statistical timing margins. LER/LWR is a fundamental scaling limiter that increases the importance of statistical design and process variability management.