line edge roughness impact on performance

**Line edge roughness (LER) impact on performance** is the **degradation in transistor behavior caused by nanoscale gate-edge fluctuations that perturb effective channel length and electric fields** - rough edges create local current crowding, leakage spread, and delay variability. **What Is LER Impact?** - **Definition**: Performance and variability effects resulting from stochastic edge deviations along patterned features. - **Origin Sources**: Resist chemistry granularity, lithography shot noise, and etch transfer imperfections. - **Electrical Consequences**: Leff variation, increased off-state leakage, and transconductance spread. - **Node Sensitivity**: Impact rises sharply at smaller gate lengths and tighter CDs. **Why LER Matters** - **Timing Variability**: Local channel fluctuations translate into path-delay uncertainty. - **Leakage Control**: Roughness-induced narrow regions increase subthreshold leakage. - **Device Matching**: Analog and SRAM cells suffer mismatch from edge randomness. - **Process Window Pressure**: Lithography and etch must control roughness at angstrom-level scales. - **EUV Challenge**: Photon statistics at EUV can amplify stochastic edge behavior. **How It Is Used in Practice** - **Metrology**: Measure LER amplitude and correlation length on critical layers. - **Compact Models**: Translate roughness metrics into electrical variation parameters. - **Mitigation**: Optimize resist-process stack, OPC, and etch smoothing conditions. LER impact on performance is **a stochastic patterning limit that converts tiny edge fluctuations into meaningful circuit-level variability** - reducing LER is a high-priority path to tighter performance distributions.