line width roughness (lwr)

Line Width Roughness (LWR) describes the statistical variation in the width of a patterned line measured along its length in semiconductor lithography. While Line Edge Roughness (LER) characterizes each edge independently, LWR captures the combined effect of roughness from both edges of a feature, reflecting how the actual critical dimension fluctuates from the target value along the length of a line. LWR is typically reported as a 3-sigma value in nanometers and is measured using critical-dimension SEM (CD-SEM) with sufficient sampling length and spatial frequency resolution. The relationship between LWR and LER depends on whether the two edges are correlated: if edges are perfectly correlated (moving in unison), LWR equals zero even with high LER; if edges are completely uncorrelated, LWR equals √2 × LER. In practice, partial correlation exists, and LWR values typically fall between these extremes. LWR is a more device-relevant metric than LER because it directly represents the variation in the physical gate length of transistors, which governs threshold voltage, drive current, and off-state leakage. At the 5 nm node and below, LWR requirements approach 1.0-1.2 nm (3-sigma), which is extraordinarily challenging to achieve. Sources of LWR include photon shot noise (particularly severe in EUV lithography), resist material properties, chemical gradient effects during development, and etch bias variations. Reducing LWR requires a holistic approach encompassing resist chemistry optimization, exposure dose management, post-develop and post-etch smoothing techniques, and computational lithography corrections. Power spectral density (PSD) analysis of LWR provides frequency-domain information that helps identify root causes and guide improvement strategies, as different sources contribute roughness at different spatial frequencies.