Logic Locking

Logic locking inserts extra key-controlled gates into a chip's design before it ever leaves for fabrication, so the netlist a foundry receives only computes the correct function when the right secret key is applied — without that key, the chip runs, but it runs wrong. A fabless design house handing a GDSII file to an outside foundry is trusting that foundry, its employees, and everyone downstream in the supply chain not to clone the design, insert a hidden trojan, or sell counterfeit extra units off an unauthorized shift — logic locking is the technique built specifically to reduce how much of that trust the foundry actually needs to be given.

Original netlist
fully correct, unlocked design
Key gates inserted at chosen nodes
XOR/XNOR gates fed by key bits
Locked netlist sent to foundry
correct function hidden behind the key
After fabrication
Correct key applied
chip functions exactly as designed
Wrong or no key
chip runs, produces wrong outputs

The mechanism is almost embarrassingly simple at the gate level, which is exactly the point. A key gate is nothing more than an XOR (or XNOR) inserted in series with an existing wire — feed it the correct key bit and it passes the original signal through unchanged; feed it the wrong bit and it inverts the signal, corrupting everything downstream of that point — scatter enough of these key gates through the design, at nodes chosen so the corruption doesn't localize to one easily-isolated area, and a foundry holding the unlocked netlist's physical layout still cannot produce a working chip without separately knowing the key.

One Key Gate, Two Outcomes an XOR inserted in series with an existing signal wire correct key bit XOR key = correct signal passes through unchanged wrong key bit XOR key = wrong signal inverted — error propagates downstream enough key gates, well-placed, and the untrusted foundry cannot clone a working chip from the layout alone

The key gets applied after fabrication, by someone the designer actually trusts, not by the foundry that made the chip. A common flow writes the correct key into a one-time-programmable fuse array or a secure non-volatile memory during test, performed back at the design house or a trusted test facility after the chip returns from the foundry — the foundry that fabricated the device never needs to know the key at all, which is exactly the point: it can mass-produce the physical silicon without ever holding the one piece of information that makes any individual chip actually work correctly.

This is one piece of a broader set of supply-chain-trust techniques, not a complete solution on its own. Split manufacturing, which fabricates front-end transistor layers at a trusted facility and sends only the back-end metal-wiring layers to a lower-trust facility, attacks the same trust problem from a different angle, and academic attacks against logic locking — including SAT-based attacks that can sometimes recover the key by exploiting how the locked and unlocked circuits must agree on a small set of test inputs — have driven an ongoing arms race between stronger locking schemes and sharper key-recovery techniques, which is why logic locking research has stayed an active field rather than a solved problem.

Read logic locking through a *withhold-the-key-not-the-chip* lens rather than an *encrypt-the-design* lens — the physical layout, the gates, and the wiring are all visible to anyone who has the GDSII file, and that was never the secret being protected; the only thing logic locking actually hides is the one piece of information needed to make all of it work correctly.

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