Contrast Maskrom Row Select Against DRAM Rascas and SRAM Wordlinebitline Architecturally

# Contrast Mask-ROM Row Select Against DRAM RAS/CAS and SRAM Word-Line/Bit-Line, Architecturally

## 1. Line Up Three Addressing Shapes Side by Side

Three memory technologies in this site's knowledge base each turn an incoming address into a readable bit, and each does it with a genuinely different addressing shape, independent of what each one's own cell stores. A mask ROM (diode- or transistor-matrix) decodes an address into one activated row line and senses the whole row's fixed pattern at once, in a single phase, with no write-back. DRAM, covered in its own series, splits the address into a row phase (RAS) that drives a shared word line and a separate column phase (CAS) that steers one sensed bit line to the output, because its own cell must also support writing a fresh charge back in in the same cycle. SRAM, covered in its own series, activates a word line that connects an array of six-transistor cells to a pair of complementary bit lines per column, sensed differentially, because its own cell holds a continuously driven latch rather than a decaying charge or a fixed connection.

Mask-ROM Addressing — Step 4 Contrast Mask-ROM Row Select Against DRAM RAS/CAS and SRAM Word-Line/Bit-Line, Architecturally MASK ROM (THIS SERIES) one row-select phase fixed pattern sensed no write-back DRAM (NAMED ONLY) RAS row phase CAS column phase write-back required SRAM (NAMED ONLY) word-line select differential bit-line pair continuously driven latch

## 2. State What the Comparison Is and Is Not Claiming

This is an architectural contrast of addressing shape only: one decode phase versus two, write-back required or not, single-ended or differential sensing. It is not a restatement of how a DRAM cell stores a charge (that belongs to the DRAM series), how an SRAM cell latches a logic state (that belongs to the SRAM series), or how a mask-ROM bit is fixed at fabrication (that belongs to `microprocessor_1971_step06`). The reason mask ROM's addressing is simpler in phase count than either alternative is structural, not incidental: a memory that is never written during normal operation has no write-back step to schedule, so its decode logic can stay a single row-select phase regardless of which device sits at the crossing (diode or transistor, per Steps 2–3).

Mask-ROM Addressing — Step 4 (cont.) Contrast Mask-ROM Row Select Against DRAM RAS/CAS and SRAM Word-Line/Bit-Line, Architecturally PHASE COUNT mask ROM: one DRAM: two (RAS, CAS) SRAM: one, differential WRITE-BACK mask ROM: never DRAM: every read SRAM: continuous latch WHY MASK ROM IS SIMPLEST never written in operation no refresh, no write-back to schedule around

Step 5 leaves addressing behind and turns to the photomask design and fabrication economics that a mask ROM's fixed bit pattern actually required before it could be read at all.

Take contrast maskrom row select against dram rascas and sram wordlinebitline architecturally further

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