Select One Row with an Address Decoder Then Read Its Diode Pattern
# Select One Row With an Address Decoder, Then Read Its Diode Pattern
## 1. Decode an Address Into One Activated Row Line
An early mask-programmed ROM organized its stored bits as a rectangular matrix: a set of horizontal row lines crossing a set of vertical column (bit) lines. An address decoder took the incoming address bits and activated exactly one row line out of the whole matrix, leaving every other row line unselected. This row-select step is the address decoder's entire job — it does not touch the bit lines directly and does not know what pattern of bits the selected row will produce.
In the diode-matrix implementation, a small junction diode was fabricated at a given row-column crossing wherever that bit position was meant to read as a 1, and no diode (an open crossing) was fabricated wherever that bit position was meant to read as a 0. When the decoder activated a row line, current could flow from that row, through the diodes present at its crossings, onto the corresponding column lines — and no current flowed at the crossings with no diode. Sensing circuitry on each column line then simply reported whether current arrived, turning the row's own diode-presence pattern directly into an output bit pattern.
## 2. Read the Whole Row's Bit Pattern in One Decode Cycle
The entire output word for that address came from a single row-activation event: every column line was sensed simultaneously, so a 1-bit, 8-bit, or wider word appeared as soon as the row's diodes finished conducting. This is the architectural core of mask-ROM addressing — one decoded row line, many parallel column sense lines, and a bit pattern that was never stored as a charge or a switch state anywhere, only as which crossings got a diode when the mask was drawn.
Contrast this, at the architecture level only, with the row-and-column addressing a one-transistor/one-capacitor DRAM cell uses: DRAM decodes a row address to drive a shared word line, then decodes a separate column address to steer one bit line's sensed charge to the output — two sequential address phases (RAS, then CAS) over a shared pin set, because DRAM's own array must also support writing a new charge back in. A diode-matrix mask ROM has no write-back step and no refresh step to coordinate, so its decode is a single row-select phase; the diode pattern itself, not a second address phase, is what makes the bit pattern what it is. Neither architecture is retold here — only the shape of how each one turns an address into a row is being contrasted.
Step 3 covers the transistor-matrix variant that eventually displaced this diode-matrix approach, and why.