metal fill semiconductor

**Metal Fill (Dummy Fill)** is the **insertion of non-functional metal shapes into sparse areas of a layout** — ensuring the metal layer density stays within foundry-specified limits that enable uniform CMP, avoid pattern density-dependent etch loading, and meet electromigration rules. **Why Metal Fill is Required** - CMP planarization is pattern-density dependent: - Dense metal areas: CMP removes metal slowly (many copper pillars support pad). - Sparse areas: CMP removes metal fast → dishing, ILD erosion. - Result without fill: Topography variation > 100nm across die → downstream litho and etch issues. - Solution: Add dummy metal to equalize pattern density → uniform CMP removal. **Fill Rules** - **Minimum density**: Typically 20–40% metal per 50×50 μm window. - **Maximum density**: Typically 70–80% (avoid CMP dishing in dense area). - **Exclusion zones**: No fill within signal routing corridors, near analog circuits, near RF components. - **Minimum/maximum size**: Fill shapes follow min CD rules, max size to avoid excessive area. **Fill Insertion Flow** 1. Analyze existing layout density in sliding window. 2. Identify under-density regions (< min%) and over-density regions (> max%). 3. Insert minimum-size fill shapes to bring under-density regions to target (50%). 4. Re-check final density — iterate if needed. 5. ERC check: Fill shapes must not violate DRC rules. **Impact on Signal Integrity** - Metal fill adds parasitic capacitance to nearby signals. - Shielded fill: Ground-tied fill → parasitic C goes to supply, not to neighbor. - Timing closure: Fill parasitic RC must be included in SPEF extraction. **Dummy Poly Fill** - Floating poly fill in non-active areas → equalize poly CMP density. - Must be electrically isolated (no gate formation) — placed outside active areas only. Metal fill is **an invisible but essential part of modern VLSI** — dense layouts with perfect DRC compliance look quite different after fill insertion, with hundreds of thousands of dummy shapes balancing CMP uniformity across every hierarchical level.