current density rules
**Design Rules and Physical Constraints** are the **comprehensive set of geometric rules that govern minimum dimensions, spacings, enclosures, and densities of all features in a chip layout** — ensuring that the designed layout can be reliably manufactured by the foundry with acceptable yield, with violations of these rules potentially causing shorts, opens, or reliability failures in the fabricated chip.
**Categories of Design Rules**
**Width and Spacing**:
- **Minimum width**: Smallest allowed line width per metal/poly layer.
- **Minimum spacing**: Smallest allowed gap between features on same layer.
- **Wide-metal spacing**: Wider wires require larger spacing (due to etch effects).
- **End-of-line (EOL) spacing**: Special rules for line tips facing each other.
**Enclosure and Extension**:
- **Via enclosure**: Metal must extend beyond via on all sides by minimum amount.
- **Contact enclosure**: Active/poly must extend beyond contact.
- **Gate extension beyond active**: Gate poly must extend past fin/diffusion edge.
**Density Rules**:
- **Minimum metal density**: Each metal layer must have > X% coverage (typically 20-30%).
- Reason: CMP requires uniform density — sparse areas dish, dense areas erode.
- **Maximum metal density**: < Y% to prevent overpolishing.
- **Fill insertion**: EDA tools insert dummy metal fill to meet density requirements.
**Advanced Node Rule Categories**
| Rule Type | Purpose | Example |
|-----------|---------|--------|
| Tip-to-tip | Prevent litho bridging at line ends | Min 2× min space at tips |
| Coloring (MP) | Assign features to patterning masks | Same-color spacing > X nm |
| Via alignment | Self-aligned via grid | Vias on allowed grid positions |
| Cut rules | Gate/fin cut placement | Min cut-to-gate spacing |
| PODE/CPODE | Poly-on-diffusion-edge | Required dummy poly at cell edges |
**DRC (Design Rule Check) Flow**
1. **EDA tool** (Calibre, ICV, Pegasus) reads GDSII layout and rule deck from foundry.
2. **Geometric engine** checks every polygon against every applicable rule.
3. **Violations flagged** with layer, rule name, and location.
4. **Fix violations**: Designer or P&R tool modifies layout.
5. **Re-run DRC** until zero violations.
**Rule Count Explosion**
- 180nm node: ~500 design rules.
- 28nm node: ~5,000 design rules.
- 7nm node: ~10,000+ design rules.
- 3nm node: ~20,000+ design rules (including multi-patterning color rules).
- Rule complexity is a major driver of EDA tool development and design cost.
Design rules are **the manufacturing contract between the designer and the foundry** — every rule exists because violating it has caused a yield or reliability failure in the past, and the exponential growth in rule count at advanced nodes reflects the increasing difficulty of manufacturing sub-10nm features reliably.